Date: Thu, 12 Jun 2003 13:14:17 +0000 From: Anthony Naggs <tony@ubik.demon.co.uk> To: Craig Boston <craig@xfoil.gank.org>, current@FreeBSD.org Cc: ticso@cicely.de Subject: Re: *IT WORKS* Re: CardBus USB 2.0 Controller (NEC uPD) Message-ID: <fSX0HMApyH6%2BIw6d@ubik.demon.co.uk> In-Reply-To: <200306112244.10466.craig@xfoil.gank.org> References: <1055260269.91337.127.camel@owen1492.uf.corelab.com> <20030611224538.GB10822@genius.tao.org.uk> <20030612002139.GT26807@cicely12.cicely.de> <200306112244.10466.craig@xfoil.gank.org>
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In article <200306112244.10466.craig@xfoil.gank.org>, Craig Boston <craig@xfoil.gank.org> writes >Believe it or not, after futzing with the debugger for hours, reading the OHCI >spec, and trying to figure out why writing to the control registers works >exactly as it should but the card seems to ignore the ED list, I decided to >try something completely crazy and put the line > >pci_enable_busmaster(self); > >near the top of ohci_attach() in ohci_pci.c > >...and it worked! I believe my first words upon seeing "ums0: <blah blah>" >were "You have GOT to be kidding me." Great news. >I'm attaching a (trivial) patch for the lazy :) Be advised, this is far from >a general solution as it probably breaks some (many?) PCI-based controllers >that don't support bus mastering. Sorry, I don't understand this comment. All OHCI, UHCI & EHCI USB controllers need PCI bus mastering in order to read & update their various lists of pending & completed transfers. Without bus mastering the system CPU has to do all this stuff in an interrupt handler. This can be quite a heavy cpu load, and is not attractive on a PC. (I've outlined this before, on hackers@. E.g. the ScanLogic SL811 needs an interrupt for every packet transfer, and Philips PHCI devices [e.g. ISP1160] needs a whole frame's worth of data to read & written every ms.) Cheers, Tony
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