Date: Mon, 14 Jul 1997 14:02:37 -0600 From: Steve Passe <smp@csn.net> To: Luigi Rizzo <luigi@labinfo.iet.unipi.it> Cc: smp@FreeBSD.ORG, hackers@FreeBSD.ORG Subject: Re: interrupt latency Message-ID: <199707142002.OAA00792@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Mon, 14 Jul 1997 20:48:59 %2B0200." <199707141849.UAA11489@labinfo.iet.unipi.it>
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Hi, > I am not familiar at all with the SMP code or the apic, but using > a hardware solution seems extremely complex. Since you are looking > at solution to improve the int latency anyways, can you consider > the following approach: > > Replace the "giant lock" with a couple of nested locks; the most > external one would only allow the posting of the hardware intr to > some cpu, but not the acquisition of the "giant lock" (i.e. the > right to enter the kernel). The nested lock is what you currently > call 'the giant lock'. The APICs don't quite work that way. There is an IO APIC connected to the external INT sources, and a local APIC in each CPU. All the APICs communicate thru a private bus. The IO APIC sends the INT to whichever CPU it determines is the best candidate based on several algorithms. for more info on the APIC as currently used, see: http://www.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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