Date: Thu, 13 Nov 2003 22:12:06 -0800 (PST) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 42308 for review Message-ID: <200311140612.hAE6C6sa098074@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=42308 Change 42308 by jmallett@jmallett_dalek on 2003/11/13 22:11:32 some xkphys cca bits, nuke some cruft nearby. Affected files ... .. //depot/projects/mips/sys/mips/include/cpuregs.h#15 edit Differences ... ==== //depot/projects/mips/sys/mips/include/cpuregs.h#15 (text+ko) ==== @@ -94,13 +94,19 @@ #define MIPS_KSEG1_TO_PHYS(x) ((vm_offset_t)(x) & MIPS_PHYS_MASK) #define MIPS_PHYS_TO_KSEG1(x) ((vm_offset_t)(x) | MIPS_KSEG1_START) -/* Map virtual address to index in mips3 r4k virtually-indexed cache */ -#define MIPS_VA_TO_CINDEX(x) \ - ((vm_offset_t)(x) & 0xffffff | MIPS_KSEG0_START) - #define MIPS_PHYS_TO_XKPHYS(cca,x) \ ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) + /* Uncached */ +#define MIPS_XKPHYS_UC (2) + /* Cacheable noncoherent */ +#define MIPS_XKPHYS_CNC (3) + /* Cacheable coherent exclusive */ +#define MIPS_XKPHYS_CCE (4) + /* Cacheable coherent exclusive on write */ +#define MIPS_XKPHYS_CCEW (5) + /* Cacheable coherent update on write */ +#define MIPS_XKPHYS_CCUW (6) /* CPU dependent mtc0 hazard hook */ #define COP0_SYNC /* nothing */
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