Date: Sun, 20 Oct 2002 18:34:53 -0400 From: "Jim McGrath" <jimmcgra@bellatlantic.net> To: "Petri Helenius" <pete@he.iki.fi>, "Don Bowman" <don@sandvine.com>, <Kevin_Stevens@pursued-with.net> Cc: <freebsd-net@FreeBSD.ORG> Subject: RE: ENOBUFS Message-ID: <NDBBKKEELKBCJJBEGDECMEIGCGAA.jimmcgra@bellatlantic.net> In-Reply-To: <046c01c27880$c7c727a0$3500080a@PHE>
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You really need Intel documentation. The Receive Interrupt Delay Value helped a lot, but in the case of the 82544, caused chip lockup under very high load. It has been a while, but the optimal value in my implementation was 22 ticks. The on chip cache is skewed in favor of receive processing, something like 70/30. In a pass through application, setting it to 50/50 helps. I'm speaking from 82543/82544 experience. Things may have changed since then. Jim > What would be the best course of action to implement optimizations > possible with later chips like 82546 to the em driver? Talk to Intel? > > Pete > > > > To Unsubscribe: send mail to majordomo@FreeBSD.org > with "unsubscribe freebsd-net" in the body of the message To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-net" in the body of the message
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