Date: Wed, 24 Jan 2018 17:52:06 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r328345 - head/sys/arm/freescale/imx Message-ID: <201801241752.w0OHq6ng062998@repo.freebsd.org>
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Author: ian Date: Wed Jan 24 17:52:06 2018 New Revision: 328345 URL: https://svnweb.freebsd.org/changeset/base/328345 Log: Reformat indentation to match other imx5/6 register definition headers, and tweak some comments. No functional changes. Modified: head/sys/arm/freescale/imx/imx_wdogreg.h Modified: head/sys/arm/freescale/imx/imx_wdogreg.h ============================================================================== --- head/sys/arm/freescale/imx/imx_wdogreg.h Wed Jan 24 17:46:20 2018 (r328344) +++ head/sys/arm/freescale/imx/imx_wdogreg.h Wed Jan 24 17:52:06 2018 (r328345) @@ -34,31 +34,31 @@ #define WDOG_CLK_FREQ 32768 #define WDOG_CR_REG 0x00 /* Control Register */ -#define WDOG_CR_WT_MASK 0xff00 /* Count of 0.5 sec */ -#define WDOG_CR_WT_SHIFT 8 -#define WDOG_CR_WDW (1 << 7) /* Suspend WDog */ -#define WDOG_CR_WDA (1 << 5) /* Don't touch ipp_wdog */ -#define WDOG_CR_SRS (1 << 4) /* Don't touch sys_reset */ -#define WDOG_CR_WDT (1 << 3) /* Assert ipp_wdog on tout */ -#define WDOG_CR_WDE (1 << 2) /* WDog Enable */ -#define WDOG_CR_WDBG (1 << 1) /* Suspend when DBG mode */ -#define WDOG_CR_WDZST (1 << 0) /* Suspend when LP mode */ +#define WDOG_CR_WT_MASK 0xff00 /* Count; 0.5 sec units */ +#define WDOG_CR_WT_SHIFT 8 +#define WDOG_CR_WDW (1u << 7) /* Suspend when in WAIT mode */ +#define WDOG_CR_WDA (1u << 5) /* Don't assert ext reset */ +#define WDOG_CR_SRS (1u << 4) /* Don't assert soft reset */ +#define WDOG_CR_WDT (1u << 3) /* Assert ext reset on timeout */ +#define WDOG_CR_WDE (1u << 2) /* Watchdog Enable */ +#define WDOG_CR_WDBG (1u << 1) /* Suspend when DBG mode */ +#define WDOG_CR_WDZST (1u << 0) /* Suspend when LP mode */ #define WDOG_SR_REG 0x02 /* Service Register */ -#define WDOG_SR_STEP1 0x5555 -#define WDOG_SR_STEP2 0xaaaa +#define WDOG_SR_STEP1 0x5555 +#define WDOG_SR_STEP2 0xaaaa #define WDOG_RSR_REG 0x04 /* Reset Status Register */ -#define WDOG_RSR_POR (1 << 4) /* Due to Power-On Reset */ -#define WDOG_RSR_TOUT (1 << 1) /* Due WDog timeout reset */ -#define WDOG_RSR_SFTW (1 << 0) /* Due Soft reset */ +#define WDOG_RSR_POR (1u << 4) /* Due to Power-On Reset */ +#define WDOG_RSR_TOUT (1u << 1) /* Due WDog timeout reset */ +#define WDOG_RSR_SFTW (1u << 0) /* Due Soft reset */ #define WDOG_ICR_REG 0x06 /* Interrupt Control Register */ -#define WDOG_ICR_WIE (1 << 15) /* Enable Interrupt */ -#define WDOG_ICR_WTIS (1 << 14) /* Interrupt has occurred */ -#define WDOG_ICR_WTCT_MASK 0x00ff -#define WDOG_ICR_WTCT_SHIFT 0 /* Interrupt hold time */ +#define WDOG_ICR_WIE (1u << 15) /* Enable Interrupt */ +#define WDOG_ICR_WTIS (1u << 14) /* Interrupt has occurred */ +#define WDOG_ICR_WTCT_MASK 0x00ff /* Interrupt lead time in 0.5s */ +#define WDOG_ICR_WTCT_SHIFT 0 /* units before reset occurs */ #define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */ -#define WDOG_MCR_PDE (1 << 0) +#define WDOG_MCR_PDE (1u << 0) /* Power-down enable */
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