Date: Thu, 30 Sep 2021 07:48:14 GMT From: Ram Kishore Vegesna <ram@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: 3bf42363b02c - main - ocs_fc: Emulex Gen 7 HBA support. Message-ID: <202109300748.18U7mEjY046433@gitrepo.freebsd.org>
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The branch main has been updated by ram: URL: https://cgit.FreeBSD.org/src/commit/?id=3bf42363b02c9bd728c92b9d9c4a5d022982a21a commit 3bf42363b02c9bd728c92b9d9c4a5d022982a21a Author: Ram Kishore Vegesna <ram@FreeBSD.org> AuthorDate: 2021-09-23 06:51:26 +0000 Commit: Ram Kishore Vegesna <ram@FreeBSD.org> CommitDate: 2021-09-30 07:31:15 +0000 ocs_fc: Emulex Gen 7 HBA support. Emulex Gen7 adapter support in ocs_fc driver. Reviewed by: mav, ken --- sys/dev/ocs_fc/ocs_hw.c | 10 ++- sys/dev/ocs_fc/ocs_os.h | 10 ++- sys/dev/ocs_fc/ocs_pci.c | 63 +++++++++++++-- sys/dev/ocs_fc/sli4.c | 200 +++++++++++++++++++++++++++++++++++++---------- sys/dev/ocs_fc/sli4.h | 80 ++++++++++++++++--- 5 files changed, 296 insertions(+), 67 deletions(-) diff --git a/sys/dev/ocs_fc/ocs_hw.c b/sys/dev/ocs_fc/ocs_hw.c index aa7d5857d9d9..c14b7a97fd97 100644 --- a/sys/dev/ocs_fc/ocs_hw.c +++ b/sys/dev/ocs_fc/ocs_hw.c @@ -272,7 +272,8 @@ ocs_hw_read_max_dump_size(ocs_hw_t *hw) int rc; /* lancer only */ - if (SLI4_IF_TYPE_LANCER_FC_ETH != sli_get_if_type(&hw->sli)) { + if ((SLI4_IF_TYPE_LANCER_FC_ETH != sli_get_if_type(&hw->sli)) && + (SLI4_IF_TYPE_LANCER_G7 != sli_get_if_type(&hw->sli))) { ocs_log_debug(hw->os, "Function only supported for I/F type 2\n"); return OCS_HW_RTN_ERROR; } @@ -414,7 +415,9 @@ ocs_hw_setup(ocs_hw_t *hw, ocs_os_handle_t os, sli4_port_type_e port_type) } /* Must be done after the workaround setup */ - if (SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(&hw->sli)) { + if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(&hw->sli)) || + (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(&hw->sli))) { + (void)ocs_hw_read_max_dump_size(hw); } @@ -6001,7 +6004,8 @@ ocs_hw_get_linkcfg(ocs_hw_t *hw, uint32_t opts, ocs_hw_port_control_cb_t cb, voi return OCS_HW_RTN_ERROR; } - if (SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(&hw->sli)) { + if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(&hw->sli)) || + (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(&hw->sli))){ return ocs_hw_get_linkcfg_lancer(hw, opts, cb, arg); } else if ((SLI4_IF_TYPE_BE3_SKH_PF == sli_get_if_type(&hw->sli)) || (SLI4_IF_TYPE_BE3_SKH_VF == sli_get_if_type(&hw->sli))) { diff --git a/sys/dev/ocs_fc/ocs_os.h b/sys/dev/ocs_fc/ocs_os.h index 5e36cca3b829..ae10b00cb465 100644 --- a/sys/dev/ocs_fc/ocs_os.h +++ b/sys/dev/ocs_fc/ocs_os.h @@ -1031,14 +1031,16 @@ typedef struct ocs_pci_reg_s { #define PCI_MAX_BAR 6 #define PCI_64BIT_BAR0 0 -#define PCI_VENDOR_EMULEX 0x10df /* Emulex */ +#define PCI_VENDOR_EMULEX 0x10df /* Emulex */ -#define PCI_PRODUCT_EMULEX_OCE16001 0xe200 /* OneCore 16Gb FC (lancer) */ -#define PCI_PRODUCT_EMULEX_OCE16002 0xe200 /* OneCore 16Gb FC (lancer) */ +#define PCI_PRODUCT_EMULEX_OCE16001 0xe200 /* OneCore 16Gb FC (lancer) */ +#define PCI_PRODUCT_EMULEX_OCE16002 0xe200 /* OneCore 16Gb FC (lancer) */ #define PCI_PRODUCT_EMULEX_LPE31004 0xe300 /* LightPulse 16Gb x 4 FC (lancer-g6) */ #define PCI_PRODUCT_EMULEX_LPE32002 0xe300 /* LightPulse 32Gb x 2 FC (lancer-g6) */ +#define PCI_PRODUCT_EMULEX_LANCER_G7 0xf400 /* LightPulse 32Gb x 4 FC (lancer-g7) */ + #define PCI_PRODUCT_EMULEX_OCE1600_VF 0xe208 -#define PCI_PRODUCT_EMULEX_OCE50102 0xe260 /* OneCore FCoE (lancer) */ +#define PCI_PRODUCT_EMULEX_OCE50102 0xe260 /* OneCore FCoE (lancer) */ #define PCI_PRODUCT_EMULEX_OCE50102_VF 0xe268 /** diff --git a/sys/dev/ocs_fc/ocs_pci.c b/sys/dev/ocs_fc/ocs_pci.c index f7e67b9bd047..8714c242a212 100644 --- a/sys/dev/ocs_fc/ocs_pci.c +++ b/sys/dev/ocs_fc/ocs_pci.c @@ -102,6 +102,9 @@ ocs_pci_probe(device_t dev) case PCI_PRODUCT_EMULEX_OCE50102: desc = "Emulex LightPulse 10GbE FCoE/NIC Adapter"; break; + case PCI_PRODUCT_EMULEX_LANCER_G7: + desc = "Emulex LightPulse G7 FC Adapter"; + break; default: return ENXIO; } @@ -112,9 +115,50 @@ ocs_pci_probe(device_t dev) } static int -ocs_map_bars(device_t dev, struct ocs_softc *ocs) +ocs_map_g7_bars(device_t dev, struct ocs_softc *ocs) { + int i, r; + uint32_t val = 0; + + for (i = 0, r = 0; i < PCI_MAX_BAR; i++) { + val = pci_read_config(dev, PCIR_BAR(i), 4); + if (!PCI_BAR_MEM(val)) { + continue; + } + if (!(val & PCIM_BAR_MEM_BASE)) { + /* no address */ + continue; + } + ocs->reg[r].rid = PCIR_BAR(i); + ocs->reg[r].res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &ocs->reg[r].rid, RF_ACTIVE); + if (ocs->reg[r].res) { + ocs->reg[r].btag = rman_get_bustag(ocs->reg[r].res); + ocs->reg[r].bhandle = rman_get_bushandle(ocs->reg[r].res); + r++; + } else { + device_printf(dev, "bus_alloc_resource failed rid=%#x\n", + ocs->reg[r].rid); + ocs_release_bus(ocs); + return ENXIO; + } + + /* + * If the 64-bit attribute is set, both this BAR and the + * next form the complete address. Skip processing the + * next BAR. + */ + if (val & PCIM_BAR_MEM_64) { + i++; + } + } + return 0; +} + +static int +ocs_map_bars(device_t dev, struct ocs_softc *ocs) +{ /* * Map PCI BAR0 register into the CPU's space. */ @@ -401,7 +445,7 @@ ocs_device_attach(ocs_t *ocs) goto fail_intr_setup; } - if(ocs_cam_attach(ocs)) { + if (ocs_cam_attach(ocs)) { device_printf(ocs->dev, "cam attach failed \n"); goto fail_intr_setup; } @@ -489,10 +533,17 @@ ocs_pci_attach(device_t dev) pci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev)); /* Map all memory BARs */ - if (ocs_map_bars(dev, ocs)) { - device_printf(dev, "Failed to map pci bars\n"); - goto release_bus; - } + if (ocs->pci_device == PCI_PRODUCT_EMULEX_LANCER_G7) { + if(ocs_map_g7_bars(dev,ocs)) { + device_printf(dev, "Failed to map pci bars\n"); + goto release_bus; + } + } else { + if (ocs_map_bars(dev, ocs)) { + device_printf(dev, "Failed to map pci bars\n"); + goto release_bus; + } + } /* create a root DMA tag for the device */ if (bus_dma_tag_create(bus_get_dma_tag(dev), diff --git a/sys/dev/ocs_fc/sli4.c b/sys/dev/ocs_fc/sli4.c index f7cea514255d..b40c4cfa2946 100644 --- a/sys/dev/ocs_fc/sli4.c +++ b/sys/dev/ocs_fc/sli4.c @@ -91,7 +91,8 @@ sli4_asic_entry_t sli4_asic_table[] = { { 0x0, 0x0c, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A0}, { 0x1, 0x0c, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A1}, { 0x3, 0x0c, SLI4_ASIC_TYPE_LANCERG6,SLI4_ASIC_REV_A3}, - + { 0x1, 0x0d, SLI4_ASIC_TYPE_LANCERG7,SLI4_ASIC_REV_A1}, + { 0x10, 0x0d, SLI4_ASIC_TYPE_LANCERG7,SLI4_ASIC_REV_B0}, { 0x00, 0x05, SLI4_ASIC_TYPE_CORSAIR, SLI4_ASIC_REV_A0}, }; @@ -124,74 +125,126 @@ const sli4_reg_t regmap[SLI4_REG_MAX][SLI4_MAX_IF_TYPES] = { /* SLI4_REG_BMBX */ { { 2, SLI4_BMBX_REG }, { 0, SLI4_BMBX_REG }, { 0, SLI4_BMBX_REG }, { 0, SLI4_BMBX_REG }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX } , { 0, SLI4_BMBX_REG }, }, /* SLI4_REG_EQCQ_DOORBELL */ { { 2, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_IF6_EQ_DOORBELL_REG } + }, + // SLI4_REG_CQ_DOORBELL + { + { 2, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG }, + { 0, SLI4_EQCQ_DOORBELL_REG }, { 0, SLI4_EQCQ_DOORBELL_REG }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_IF6_CQ_DOORBELL_REG } }, /* SLI4_REG_FCOE_RQ_DOORBELL */ { { 2, SLI4_RQ_DOORBELL_REG }, { 0, SLI4_RQ_DOORBELL_REG }, { 0, SLI4_RQ_DOORBELL_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_IF6_RQ_DOORBELL_REG } }, /* SLI4_REG_IO_WQ_DOORBELL */ { - { 2, SLI4_IO_WQ_DOORBELL_REG }, { 0, SLI4_IO_WQ_DOORBELL_REG }, { 0, SLI4_IO_WQ_DOORBELL_REG }, { UINT32_MAX, UINT32_MAX }, - }, + { 2, SLI4_IO_WQ_DOORBELL_REG }, { 0, SLI4_IO_WQ_DOORBELL_REG }, + { 0, SLI4_IO_WQ_DOORBELL_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_IF6_WQ_DOORBELL_REG } + }, /* SLI4_REG_MQ_DOORBELL */ { { 2, SLI4_MQ_DOORBELL_REG }, { 0, SLI4_MQ_DOORBELL_REG }, { 0, SLI4_MQ_DOORBELL_REG }, { 0, SLI4_MQ_DOORBELL_REG }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_IF6_MQ_DOORBELL_REG } }, /* SLI4_REG_PHYSDEV_CONTROL */ { - { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { 0, SLI4_PHSDEV_CONTROL_REG_23 }, { 0, SLI4_PHSDEV_CONTROL_REG_23 }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_PHSDEV_CONTROL_REG_236 }, { 0, SLI4_PHSDEV_CONTROL_REG_236 }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_PHSDEV_CONTROL_REG_236 } }, /* SLI4_REG_SLIPORT_CONTROL */ { - { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { 0, SLI4_SLIPORT_CONTROL_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_SLIPORT_CONTROL_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_SLIPORT_CONTROL_REG }, }, /* SLI4_REG_SLIPORT_ERROR1 */ { - { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { 0, SLI4_SLIPORT_ERROR1 }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_SLIPORT_ERROR1 }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_SLIPORT_ERROR1 }, }, /* SLI4_REG_SLIPORT_ERROR2 */ { - { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { 0, SLI4_SLIPORT_ERROR2 }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_SLIPORT_ERROR2 }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_SLIPORT_ERROR2 }, }, /* SLI4_REG_SLIPORT_SEMAPHORE */ { { 1, SLI4_PORT_SEMAPHORE_REG_0 }, { 0, SLI4_PORT_SEMAPHORE_REG_1 }, - { 0, SLI4_PORT_SEMAPHORE_REG_23 }, { 0, SLI4_PORT_SEMAPHORE_REG_23 }, + { 0, SLI4_PORT_SEMAPHORE_REG_236 }, { 0, SLI4_PORT_SEMAPHORE_REG_236 }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_PORT_SEMAPHORE_REG_236 }, }, /* SLI4_REG_SLIPORT_STATUS */ { - { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { 0, SLI4_PORT_STATUS_REG_23 }, { 0, SLI4_PORT_STATUS_REG_23 }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_PORT_STATUS_REG_236 }, { 0, SLI4_PORT_STATUS_REG_236 }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_PORT_STATUS_REG_236 }, }, /* SLI4_REG_UERR_MASK_HI */ { - { 0, SLI4_UERR_MASK_HIGH_REG }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_UERR_MASK_HIGH_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX } }, /* SLI4_REG_UERR_MASK_LO */ { - { 0, SLI4_UERR_MASK_LOW_REG }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_UERR_MASK_LOW_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX } }, /* SLI4_REG_UERR_STATUS_HI */ { - { 0, SLI4_UERR_STATUS_HIGH_REG }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_UERR_STATUS_HIGH_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX } }, /* SLI4_REG_UERR_STATUS_LO */ { - { 0, SLI4_UERR_STATUS_LOW_REG }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 0, SLI4_UERR_STATUS_LOW_REG }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX } }, /* SLI4_REG_SW_UE_CSR1 */ { - { 1, SLI4_SW_UE_CSR1}, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_SW_UE_CSR1}, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX } }, /* SLI4_REG_SW_UE_CSR2 */ { - { 1, SLI4_SW_UE_CSR2}, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { 1, SLI4_SW_UE_CSR2}, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX }, { UINT32_MAX, UINT32_MAX }, + { UINT32_MAX, UINT32_MAX } }, }; @@ -1739,6 +1792,7 @@ sli_cmd_common_create_cq(sli4_t *sli4, void *buf, size_t size, cmd_size = sizeof(sli4_req_common_create_cq_v0_t) + (8 * num_pages); break; case SLI4_IF_TYPE_LANCER_FC_ETH: + case SLI4_IF_TYPE_LANCER_G7: n_cqe = qmem->size / SLI4_CQE_BYTES; switch (n_cqe) { case 256: @@ -1814,6 +1868,7 @@ sli_cmd_common_create_cq(sli4_t *sli4, void *buf, size_t size, break; case SLI4_IF_TYPE_LANCER_FC_ETH: + case SLI4_IF_TYPE_LANCER_G7: { cqv2 = (sli4_req_common_create_cq_v2_t *)((uint8_t *)buf + sli_config_off); cqv2->hdr.opcode = SLI4_OPC_COMMON_CREATE_CQ; @@ -1821,6 +1876,9 @@ sli_cmd_common_create_cq(sli4_t *sli4, void *buf, size_t size, cqv2->hdr.version = 2; cqv2->hdr.request_length = cmd_size - sizeof(sli4_req_hdr_t); + if (if_type == SLI4_IF_TYPE_LANCER_G7) + cqv2->autovalid = TRUE; + cqv2->page_size = page_size; /* valid values for number of pages: 1, 2, 4, 8 (sec 4.4.3) */ @@ -1993,6 +2051,10 @@ sli_cmd_common_create_eq(sli4_t *sli4, void *buf, size_t size, ocs_dma_t *qmem, eq->hdr.subsystem = SLI4_SUBSYSTEM_COMMON; eq->hdr.request_length = sizeof(sli4_req_common_create_eq_t) - sizeof(sli4_req_hdr_t); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) { + eq->hdr.version = 2; + eq->autovalid = TRUE; + } /* valid values for number of pages: 1, 2, 4 (sec 4.4.3) */ eq->num_pages = qmem->size / SLI_PAGE_SIZE; switch (eq->num_pages) { @@ -2445,6 +2507,7 @@ sli_cmd_common_get_port_name(sli4_t *sli4, void *buf, size_t size) break; case SLI4_IF_TYPE_LANCER_FC_ETH: case SLI4_IF_TYPE_LANCER_RDMA: + case SLI4_IF_TYPE_LANCER_G7: version = 1; break; default: @@ -3309,6 +3372,7 @@ sli_fw_init(sli4_t *sli4) } break; case SLI4_IF_TYPE_LANCER_FC_ETH: + case SLI4_IF_TYPE_LANCER_G7: #if BYTE_ORDER == LITTLE_ENDIAN endian = SLI4_SLIPORT_CONTROL_LITTLE_ENDIAN; #else @@ -3387,11 +3451,17 @@ sli_queue_doorbell(sli4_t *sli4, sli4_queue_t *q) switch (q->type) { case SLI_QTYPE_EQ: - val = sli_eq_doorbell(q->n_posted, q->id, FALSE); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) + val = sli_iftype6_eq_doorbell(q->n_posted, q->id, FALSE); + else + val = sli_eq_doorbell(q->n_posted, q->id, FALSE); ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); break; case SLI_QTYPE_CQ: - val = sli_cq_doorbell(q->n_posted, q->id, FALSE); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) + val = sli_iftype6_cq_doorbell(q->n_posted, q->id, FALSE); + else + val = sli_cq_doorbell(q->n_posted, q->id, FALSE); ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); break; case SLI_QTYPE_MQ: @@ -3435,7 +3505,13 @@ sli_queue_doorbell(sli4_t *sli4, sli4_queue_t *q) break; } case SLI_QTYPE_WQ: - val = SLI4_WQ_DOORBELL(q->n_posted, q->index, q->id); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) { + val = SLI4_WQ_DOORBELL(q->n_posted, 0, q->id); + } else { + /* For iftype = 2 and 3, q->index value is ignored */ + val = SLI4_WQ_DOORBELL(q->n_posted, q->index, q->id); + } + ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); break; default: @@ -3627,7 +3703,7 @@ sli_get_config(sli4_t *sli4) sli4->config.extent[SLI_RSRC_FCOE_RPI].size = read_config->rpi_count; sli4->config.extent[SLI_RSRC_FCOE_XRI].base[0] = read_config->xri_base; - sli4->config.extent[SLI_RSRC_FCOE_XRI].size = read_config->xri_count; + sli4->config.extent[SLI_RSRC_FCOE_XRI].size = OCS_MIN(255,read_config->xri_count); sli4->config.extent[SLI_RSRC_FCOE_FCFI].base[0] = 0; sli4->config.extent[SLI_RSRC_FCOE_FCFI].size = read_config->fcfi_count; @@ -3988,7 +4064,8 @@ sli_setup(sli4_t *sli4, ocs_os_handle_t os, sli4_port_type_e port_type) sli4->if_type = sli_intf_if_type(sli_intf); - if (SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type) { + if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type) || + (SLI4_IF_TYPE_LANCER_G7 == sli4->if_type)) { ocs_log_debug(os, "status=%#x error1=%#x error2=%#x\n", sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS), sli_reg_read(sli4, SLI4_REG_SLIPORT_ERROR1), @@ -4320,6 +4397,11 @@ __sli_queue_init(sli4_t *sli4, sli4_queue_t *q, uint32_t qtype, /* Limit to hwf the queue size per interrupt */ q->proc_limit = n_entries / 2; + if ( (q->type == SLI_QTYPE_EQ) || (q->type == SLI_QTYPE_CQ) ) { + /* For prism, phase will be flipped after a sweep through eq and cq */ + q->phase = 1; + } + switch(q->type) { case SLI_QTYPE_EQ: q->posted_limit = q->length / 2; @@ -4381,13 +4463,13 @@ __sli_create_queue(sli4_t *sli4, sli4_queue_t *q) switch (q->type) { case SLI_QTYPE_EQ: /* No doorbell information in response for EQs */ - q->doorbell_offset = regmap[SLI4_REG_EQCQ_DOORBELL][sli4->if_type].off; - q->doorbell_rset = regmap[SLI4_REG_EQCQ_DOORBELL][sli4->if_type].rset; + q->doorbell_offset = regmap[SLI4_REG_EQ_DOORBELL][sli4->if_type].off; + q->doorbell_rset = regmap[SLI4_REG_EQ_DOORBELL][sli4->if_type].rset; break; case SLI_QTYPE_CQ: /* No doorbell information in response for CQs */ - q->doorbell_offset = regmap[SLI4_REG_EQCQ_DOORBELL][sli4->if_type].off; - q->doorbell_rset = regmap[SLI4_REG_EQCQ_DOORBELL][sli4->if_type].rset; + q->doorbell_offset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].off; + q->doorbell_rset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].rset; break; case SLI_QTYPE_MQ: /* No doorbell information in response for MQs */ @@ -4694,6 +4776,9 @@ sli_cq_alloc_set(sli4_t *sli4, sli4_queue_t *qs[], uint32_t num_cqs, req->arm = FALSE; req->num_cq_req = num_cqs; + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) + req->autovalid = TRUE; + /* Fill page addresses of all the CQs. */ for (i = 0; i < num_cqs; i++) { req->eq_id[i] = eqs[i]->id; @@ -4724,8 +4809,8 @@ sli_cq_alloc_set(sli4_t *sli4, sli4_queue_t *qs[], uint32_t num_cqs, /* Fill the resp cq ids. */ for (i = 0; i < num_cqs; i++) { qs[i]->id = res->q_id + i; - qs[i]->doorbell_offset = regmap[SLI4_REG_EQCQ_DOORBELL][sli4->if_type].off; - qs[i]->doorbell_rset = regmap[SLI4_REG_EQCQ_DOORBELL][sli4->if_type].rset; + qs[i]->doorbell_offset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].off; + qs[i]->doorbell_rset = regmap[SLI4_REG_CQ_DOORBELL][sli4->if_type].rset; } } @@ -4922,9 +5007,13 @@ sli_queue_eq_arm(sli4_t *sli4, sli4_queue_t *q, uint8_t arm) uint32_t val = 0; ocs_lock(&q->lock); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) + val = sli_iftype6_eq_doorbell(q->n_posted, q->id, arm); + else val = sli_eq_doorbell(q->n_posted, q->id, arm); - ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); - q->n_posted = 0; + + ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); + q->n_posted = 0; ocs_unlock(&q->lock); return 0; @@ -4949,12 +5038,18 @@ sli_queue_arm(sli4_t *sli4, sli4_queue_t *q, uint8_t arm) switch (q->type) { case SLI_QTYPE_EQ: - val = sli_eq_doorbell(q->n_posted, q->id, arm); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) + val = sli_iftype6_eq_doorbell(q->n_posted, q->id, arm); + else + val = sli_eq_doorbell(q->n_posted, q->id, arm); ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); q->n_posted = 0; break; case SLI_QTYPE_CQ: - val = sli_cq_doorbell(q->n_posted, q->id, arm); + if (sli4->if_type == SLI4_IF_TYPE_LANCER_G7) + val = sli_iftype6_cq_doorbell(q->n_posted, q->id, arm); + else + val = sli_cq_doorbell(q->n_posted, q->id, arm); ocs_reg_write32(sli4->os, q->doorbell_rset, q->doorbell_offset, val); q->n_posted = 0; break; @@ -5069,10 +5164,11 @@ static uint8_t sli_queue_entry_is_valid(sli4_queue_t *q, uint8_t *qe, uint8_t clear) { uint8_t valid = FALSE; + uint8_t valid_bit_set = 0; switch (q->type) { case SLI_QTYPE_EQ: - valid = ((sli4_eqe_t *)qe)->vld; + valid = (((sli4_eqe_t *)qe)->vld == q->phase) ? 1 : 0; if (valid && clear) { ((sli4_eqe_t *)qe)->vld = 0; } @@ -5082,7 +5178,10 @@ sli_queue_entry_is_valid(sli4_queue_t *q, uint8_t *qe, uint8_t clear) * For both MCQE and WCQE/RCQE, the valid bit * is bit 31 of dword 3 (0 based) */ - valid = (qe[15] & 0x80) != 0; + valid_bit_set = (qe[15] & 0x80) != 0; + if (valid_bit_set == q->phase) + valid = 1; + if (valid & clear) { qe[15] &= ~0x80; } @@ -5099,6 +5198,7 @@ sli_queue_entry_is_valid(sli4_queue_t *q, uint8_t *qe, uint8_t clear) } if (clear) { + ocs_dma_sync(&q->dma, OCS_DMASYNC_PREWRITE); } @@ -5122,6 +5222,7 @@ sli_queue_read(sli4_t *sli4, sli4_queue_t *q, uint8_t *entry) uint8_t *qe = q->dma.virt; uint32_t *qindex = NULL; + uint8_t clear = (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4)) ? FALSE : TRUE; if (SLI_QTYPE_MQ == q->type) { qindex = &q->u.r_idx; } else { @@ -5134,7 +5235,7 @@ sli_queue_read(sli4_t *sli4, sli4_queue_t *q, uint8_t *entry) qe += *qindex * q->size; - if (!sli_queue_entry_is_valid(q, qe, TRUE)) { + if (!sli_queue_entry_is_valid(q, qe, clear)) { ocs_unlock(&q->lock); return -1; } @@ -5165,6 +5266,13 @@ sli_queue_read(sli4_t *sli4, sli4_queue_t *q, uint8_t *entry) *qindex = (*qindex + 1) & (q->length - 1); if (SLI_QTYPE_MQ != q->type) { q->n_posted++; + /* + * For prism, the phase value will be used to check the validity of eq/cq entries. + * The value toggles after a complete sweep through the queue. + */ + if ((SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4)) && (*qindex == 0)) { + q->phase ^= (uint16_t) 0x1; + } } break; default: @@ -5487,8 +5595,9 @@ int32_t sli_raise_ue(sli4_t *sli4, uint8_t dump) ocs_log_test(sli4->os, "invalid asic type %d\n", sli_get_asic_type(sli4)); return -1; } - } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(sli4)) { - if (dump == FDD) { + } else if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(sli4)) || + (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4))) { + if (FDD == dump) { sli_reg_write(sli4, SLI4_REG_SLIPORT_CONTROL, SLI4_SLIPORT_CONTROL_FDD | SLI4_SLIPORT_CONTROL_IP); } else { uint32_t value = SLI4_PHYDEV_CONTROL_FRST; @@ -5532,7 +5641,8 @@ int32_t sli_dump_is_ready(sli4_t *sli4) rc = 1; } - } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(sli4)) { + } else if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli_get_if_type(sli4)) || + (SLI4_IF_TYPE_LANCER_G7 == sli_get_if_type(sli4))) { /* * Ensure that the port is ready AND the mailbox is * ready before signaling that the dump is ready to go. @@ -5542,7 +5652,7 @@ int32_t sli_dump_is_ready(sli4_t *sli4) if ((bmbx_val & SLI4_BMBX_RDY) && SLI4_PORT_STATUS_READY(port_val)) { - if(SLI4_PORT_STATUS_DUMP_PRESENT(port_val)) { + if(SLI4_PORT_STATUS_DUMP_PRESENT(port_val)) { rc = 1; }else if( SLI4_PORT_STATUS_FDP_PRESENT(port_val)) { rc = 2; @@ -5571,7 +5681,8 @@ int32_t sli_dump_is_present(sli4_t *sli4) uint32_t val; uint32_t ready; - if (SLI4_IF_TYPE_LANCER_FC_ETH != sli_get_if_type(sli4)) { + if ((SLI4_IF_TYPE_LANCER_FC_ETH != sli_get_if_type(sli4)) && + (SLI4_IF_TYPE_LANCER_G7 != sli_get_if_type(sli4))) { ocs_log_test(sli4->os, "Function only supported for I/F type 2"); return -1; } @@ -5658,7 +5769,8 @@ int32_t sli_fw_error_status(sli4_t *sli4) (uerr_mask_hi & uerr_status_hi) != 0) { rc = 1; } - } else if ((SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type)) { + } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type || + SLI4_IF_TYPE_LANCER_G7 == sli4->if_type) { uint32_t sliport_status; sliport_status = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS); @@ -5692,9 +5804,10 @@ sli_fw_ready(sli4_t *sli4) SLI4_IF_TYPE_BE3_SKH_VF == sli4->if_type) { val = sli_reg_read(sli4, SLI4_REG_SLIPORT_SEMAPHORE); rc = ((SLI4_PORT_SEMAPHORE_STATUS_POST_READY == - SLI4_PORT_SEMAPHORE_PORT(val)) && - (!SLI4_PORT_SEMAPHORE_IN_ERR(val)) ? 1 : 0); - } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type) { + SLI4_PORT_SEMAPHORE_PORT(val)) && + (!SLI4_PORT_SEMAPHORE_IN_ERR(val)) ? 1 : 0); + } else if (SLI4_IF_TYPE_LANCER_FC_ETH == sli4->if_type || + SLI4_IF_TYPE_LANCER_G7 == sli4->if_type) { val = sli_reg_read(sli4, SLI4_REG_SLIPORT_STATUS); rc = (SLI4_PORT_STATUS_READY(val) ? 1 : 0); } @@ -5726,6 +5839,7 @@ int32_t sli_link_is_configurable(sli4_t *sli) rc = 1; break; case SLI4_ASIC_TYPE_LANCERG6: + case SLI4_ASIC_TYPE_LANCERG7: case SLI4_ASIC_TYPE_BE3: default: rc = 0; @@ -5755,7 +5869,7 @@ int32_t sli_link_is_configurable(sli4_t *sli) */ int32_t sli_cmd_fcoe_wq_create(sli4_t *sli4, void *buf, size_t size, - ocs_dma_t *qmem, uint16_t cq_id, uint16_t ulp) + ocs_dma_t *qmem, uint16_t cq_id, uint16_t ulp) { sli4_req_fcoe_wq_create_t *wq = NULL; uint32_t sli_config_off = 0; diff --git a/sys/dev/ocs_fc/sli4.h b/sys/dev/ocs_fc/sli4.h index 4d0c8013b063..54e1915a715c 100644 --- a/sys/dev/ocs_fc/sli4.h +++ b/sys/dev/ocs_fc/sli4.h @@ -114,7 +114,8 @@ sli_page_count(size_t bytes, uint32_t page_size) #define SLI4_IF_TYPE_BE3_SKH_VF 1 #define SLI4_IF_TYPE_LANCER_FC_ETH 2 #define SLI4_IF_TYPE_LANCER_RDMA 3 -#define SLI4_MAX_IF_TYPES 4 +#define SLI4_IF_TYPE_LANCER_G7 6 +#define SLI4_MAX_IF_TYPES 7 /** * @brief ASIC_ID - SLI ASIC Type and Revision Register @@ -150,7 +151,7 @@ sli_page_count(size_t bytes, uint32_t page_size) /** * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register */ -#define SLI4_EQCQ_DOORBELL_REG 0x120 +#define SLI4_EQCQ_DOORBELL_REG 0x120 #define SLI4_EQCQ_DOORBELL_CI BIT(9) #define SLI4_EQCQ_DOORBELL_QT BIT(10) #define SLI4_EQCQ_DOORBELL_ARM BIT(29) @@ -162,6 +163,8 @@ sli_page_count(size_t bytes, uint32_t page_size) #define SLI4_EQCQ_EQ_ID_MASK_LO 0x01ff #define SLI4_EQCQ_CQ_ID_MASK_LO 0x03ff #define SLI4_EQCQ_EQCQ_ID_MASK_HI 0xf800 +#define SLI4_IF6_EQ_DOORBELL_REG 0x120 +#define SLI4_IF6_CQ_DOORBELL_REG 0xC0 /** * @brief SLIPORT_CONTROL - SLI Port Control Register @@ -257,10 +260,56 @@ static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t a return reg; } +static inline uint32_t sli_iftype6_eq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) +{ + uint32_t reg = 0; +#if BYTE_ORDER == LITTLE_ENDIAN + struct { + uint32_t eq_id:12, + :4, /* clear interrupt */ + number_popped:13, + arm:1, + :1, + io:1; + } * eq_doorbell = (void *)® +#else +#error big endian version not defined +#endif + + eq_doorbell->eq_id = id; + eq_doorbell->number_popped = n_popped; + eq_doorbell->arm = arm; + + return reg; +} + +static inline uint32_t sli_iftype6_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t arm) +{ + uint32_t reg = 0; +#if BYTE_ORDER == LITTLE_ENDIAN + struct { + uint32_t cq_id:16, + number_popped:13, + arm:1, + :1, + se:1; + } * cq_doorbell = (void *)® +#else +#error big endian version not defined +#endif + + cq_doorbell->cq_id = id; + cq_doorbell->number_popped = n_popped; + cq_doorbell->arm = arm; + + return reg; +} + /** * @brief MQ_DOORBELL - MQ Doorbell Register */ -#define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ +#define SLI4_MQ_DOORBELL_REG 0x0140 /* register offset */ +#define SLI4_IF6_MQ_DOORBELL_REG 0x0160 /* register offset if_type = 6 */ #define SLI4_MQ_DOORBELL_NUM_SHIFT 16 #define SLI4_MQ_DOORBELL_NUM_MASK 0x3fff #define SLI4_MQ_DOORBELL_ID_MASK 0xffff @@ -270,7 +319,8 @@ static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t a /** * @brief RQ_DOORBELL - RQ Doorbell Register */ -#define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ +#define SLI4_RQ_DOORBELL_REG 0x0a0 /* register offset */ +#define SLI4_IF6_RQ_DOORBELL_REG 0x0080 /* register offset of if_type = 6 */ #define SLI4_RQ_DOORBELL_NUM_SHIFT 16 #define SLI4_RQ_DOORBELL_NUM_MASK 0x3fff #define SLI4_RQ_DOORBELL_ID_MASK 0xffff @@ -280,7 +330,8 @@ static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t a /** * @brief WQ_DOORBELL - WQ Doorbell Register */ -#define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ +#define SLI4_IO_WQ_DOORBELL_REG 0x040 /* register offset */ +#define SLI4_IF6_WQ_DOORBELL_REG 0x040 /* register offset for if_type = 6 */ #define SLI4_WQ_DOORBELL_IDX_SHIFT 16 #define SLI4_WQ_DOORBELL_IDX_MASK 0x00ff #define SLI4_WQ_DOORBELL_NUM_SHIFT 24 @@ -295,7 +346,7 @@ static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t a */ #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */ #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */ -#define SLI4_PORT_SEMAPHORE_REG_23 0x0400 /** register offset Interface Type 2 + 3 */ +#define SLI4_PORT_SEMAPHORE_REG_236 0x0400 /** register offset Interface Type 2 + 3 + 6*/ #define SLI4_PORT_SEMAPHORE_PORT_MASK 0x0000ffff #define SLI4_PORT_SEMAPHORE_PORT(r) ((r) & SLI4_PORT_SEMAPHORE_PORT_MASK) #define SLI4_PORT_SEMAPHORE_HOST_MASK 0x00ff0000 @@ -319,7 +370,7 @@ static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t a * @brief SLIPORT_STATUS - SLI Port Status Register */ -#define SLI4_PORT_STATUS_REG_23 0x0404 /** register offset Interface Type 2 + 3 */ +#define SLI4_PORT_STATUS_REG_236 0x0404 /** register offset Interface Type 2 + 3 + 6*/ #define SLI4_PORT_STATUS_FDP BIT(21) /** function specific dump present */ #define SLI4_PORT_STATUS_RDY BIT(23) /** ready */ #define SLI4_PORT_STATUS_RN BIT(24) /** reset needed */ @@ -332,7 +383,7 @@ static inline uint32_t sli_cq_doorbell(uint16_t n_popped, uint16_t id, uint8_t a #define SLI4_PORT_STATUS_DUMP_PRESENT(r) ((r) & SLI4_PORT_STATUS_DIP) #define SLI4_PORT_STATUS_FDP_PRESENT(r) ((r) & SLI4_PORT_STATUS_FDP) -#define SLI4_PHSDEV_CONTROL_REG_23 0x0414 /** register offset Interface Type 2 + 3 */ +#define SLI4_PHSDEV_CONTROL_REG_236 0x0414 /** register offset Interface Type 2 + 3 + 6*/ #define SLI4_PHYDEV_CONTROL_DRST BIT(0) /** physical device reset */ #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */ #define SLI4_PHYDEV_CONTROL_DD BIT(2) /** diagnostic dump */ @@ -1557,7 +1608,8 @@ typedef struct sli4_req_common_create_cq_v2_s { clswm:2, nodelay:1, autovalid:1, - :11, + :9, + cqe_size:2, cqecnt:2, valid:1, :1, @@ -1691,7 +1743,8 @@ typedef struct sli4_req_common_create_eq_s { #if BYTE_ORDER == LITTLE_ENDIAN uint32_t num_pages:16, :16; - uint32_t :29, + uint32_t :28, + autovalid:1, valid:1, :1, eqesz:1; @@ -2960,7 +3013,8 @@ typedef struct sli4_acqe_s { */ typedef enum { SLI4_REG_BMBX, - SLI4_REG_EQCQ_DOORBELL, + SLI4_REG_EQ_DOORBELL, + SLI4_REG_CQ_DOORBELL, SLI4_REG_FCOE_RQ_DOORBELL, SLI4_REG_IO_WQ_DOORBELL, SLI4_REG_MQ_DOORBELL, @@ -3027,6 +3081,9 @@ typedef struct sli4_queue_s { uint32_t max_num_processed; time_t max_process_time; + uint16_t phase; /** For if_type = 6, this value toggle for each iteration + of the queue, a queue entry is valid when a cqe valid + bit matches this value */ /* Type specific gunk */ union { uint32_t r_idx; /** "read" index (MQ only) */ @@ -3131,6 +3188,7 @@ typedef enum { SLI4_ASIC_TYPE_LANCER, SLI4_ASIC_TYPE_CORSAIR, SLI4_ASIC_TYPE_LANCERG6, + SLI4_ASIC_TYPE_LANCERG7 } sli4_asic_type_e; typedef enum {
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