Date: Thu, 18 Sep 2008 20:00:52 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 150038 for review Message-ID: <200809182000.m8IK0qgJ070345@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=150038 Change 150038 by imp@imp_paco-paco on 2008/09/18 20:00:26 IFC @150036 Affected files ... .. //depot/projects/mips2/src/share/misc/committers-src.dot#10 integrate .. //depot/projects/mips2/src/sys/amd64/amd64/identcpu.c#9 integrate .. //depot/projects/mips2/src/sys/i386/i386/identcpu.c#10 integrate .. //depot/projects/mips2/src/sys/sparc64/pci/psycho.c#11 integrate .. //depot/projects/mips2/src/sys/sparc64/pci/psychoreg.h#5 integrate Differences ... ==== //depot/projects/mips2/src/share/misc/committers-src.dot#10 (text+ko) ==== @@ -1,4 +1,4 @@ -# $FreeBSD: src/share/misc/committers-src.dot,v 1.84 2008/08/22 18:52:27 jhb Exp $ +# $FreeBSD: src/share/misc/committers-src.dot,v 1.85 2008/09/18 17:32:13 zec Exp $ # This file is meant to list all FreeBSD src committers and describe the # mentor-mentee relationships between them. @@ -178,6 +178,7 @@ wsalamon [label="Wayne Salamon\nwsalamon@FreeBSD.org\n2005/06/25"] yar [label="Yar Tikhiy\nyar@FreeBSD.org\n2001/03/25"] yongari [label="Pyun YongHyeon\nyongari@FreeBSD.org\n2004/08/01"] +zec [label="Marko Zec\nzec@FreeBSD.org\n2008/06/22"] # Pseudo target representing rev 1.1 of commit.allow day1 [label="Birth of FreeBSD"] @@ -313,6 +314,7 @@ julian -> davidxu julian -> archie julian -> adrian +julian -> zec kib -> lulf ==== //depot/projects/mips2/src/sys/amd64/amd64/identcpu.c#9 (text+ko) ==== @@ -39,7 +39,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/amd64/amd64/identcpu.c,v 1.159 2008/05/23 04:03:52 alc Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/identcpu.c,v 1.160 2008/09/18 18:51:32 stas Exp $"); #include "opt_cpu.h" @@ -249,8 +249,8 @@ "\030POPCNT" "\031<b24>" "\032<b25>" - "\033<b26>" - "\034<b27>" + "\033XSAVE" + "\034OSXSAVE" "\035<b28>" "\036<b29>" "\037<b30>" ==== //depot/projects/mips2/src/sys/i386/i386/identcpu.c#10 (text+ko) ==== @@ -39,7 +39,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/i386/i386/identcpu.c,v 1.186 2008/09/17 20:45:18 jhb Exp $"); +__FBSDID("$FreeBSD: src/sys/i386/i386/identcpu.c,v 1.187 2008/09/18 18:51:32 stas Exp $"); #include "opt_cpu.h" @@ -743,8 +743,8 @@ "\030POPCNT" "\031<b24>" "\032<b25>" - "\033<b26>" - "\034<b27>" + "\033XSAVE" + "\034OSXSAVE" "\035<b28>" "\036<b29>" "\037<b30>" ==== //depot/projects/mips2/src/sys/sparc64/pci/psycho.c#11 (text+ko) ==== @@ -31,7 +31,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/sparc64/pci/psycho.c,v 1.79 2008/08/24 16:22:04 marius Exp $"); +__FBSDID("$FreeBSD: src/sys/sparc64/pci/psycho.c,v 1.80 2008/09/18 19:45:22 marius Exp $"); /* * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' @@ -369,9 +369,6 @@ sc->sc_mtx = osc->sc_mtx; } - /* Clear PCI AFSR. */ - PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK); - csr = PSYCHO_READ8(sc, PSR_CS); ver = PSYCHO_GCSR_VERS(csr); sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ @@ -425,7 +422,7 @@ break; } - csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4; + csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); #ifdef PSYCHO_DEBUG device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", @@ -533,46 +530,7 @@ "controller for INO %d", __func__, n); } - /* - * Establish handlers for interesting interrupts... - * - * XXX We need to remember these and remove this to support - * hotplug on the UPA/FHC bus. - * - * XXX Not all controllers have these, but installing them - * is better than trying to sort through this mess. - */ - psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); - psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); -#ifdef DEBUGGER_ON_POWERFAIL - psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, - NULL); -#else - psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, - (driver_intr_t *)psycho_powerfail); -#endif - /* Psycho-specific initialization */ if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { - /* - * Hummingbirds/Sabres do not have the following two - * interrupts. - */ - - /* - * The spare hardware interrupt is used for the - * over-temperature interrupt. - */ - psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, - NULL, psycho_overtemp); -#ifdef PSYCHO_MAP_WAKEUP - /* - * psycho_wakeup() doesn't do anything useful right - * now. - */ - psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, - psycho_wakeup, NULL); -#endif /* PSYCHO_MAP_WAKEUP */ - /* Initialize the counter-timer. */ sparc64_counter_init(device_get_nameunit(dev), rman_get_bustag(sc->sc_mem_res), @@ -612,14 +570,6 @@ iommu_reset(sc->sc_is); } - /* - * Register a PCI bus error interrupt handler according to which - * half this is. Hummingbird/Sabre don't have a PCI bus B error - * interrupt but they are also only used for PCI bus A. - */ - psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : - PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); - /* Allocate our tags. */ sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); @@ -643,11 +593,61 @@ prop_array[0], prop_array[1], prop_array[0]); sc->sc_pci_secbus = prop_array[0]; - /* Clear PCI status error bits. */ + /* Clear any pending PCI error bits. */ PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, - PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT | - PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT | - PCIM_STATUS_PERRREPORT, 2); + PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, + PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); + PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); + PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); + + if (osc == NULL) { + /* + * Establish handlers for interesting interrupts... + * + * XXX We need to remember these and remove this to support + * hotplug on the UPA/FHC bus. + * + * XXX Not all controllers have these, but installing them + * is better than trying to sort through this mess. + */ + psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); + psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); +#ifdef DEBUGGER_ON_POWERFAIL + psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, + NULL); +#else + psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, + (driver_intr_t *)psycho_powerfail); +#endif + if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { + /* + * Hummingbirds/Sabres do not have the following two + * interrupts. + */ + + /* + * The spare hardware interrupt is used for the + * over-temperature interrupt. + */ + psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, + NULL, psycho_overtemp); +#ifdef PSYCHO_MAP_WAKEUP + /* + * psycho_wakeup() doesn't do anything useful right + * now. + */ + psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, + psycho_wakeup, NULL); +#endif /* PSYCHO_MAP_WAKEUP */ + } + } + /* + * Register a PCI bus error interrupt handler according to which + * half this is. Hummingbird/Sabre don't have a PCI bus B error + * interrupt but they are also only used for PCI bus A. + */ + psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : + PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); /* * Set the latency timer register as this isn't always done by the @@ -808,7 +808,7 @@ device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " "AFSR %#lx\n", (u_long)afar, (u_long)afsr); /* Clear the error bits that we caught. */ - PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK); + PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); mtx_unlock_spin(sc->sc_mtx); return (FILTER_HANDLED); } ==== //depot/projects/mips2/src/sys/sparc64/pci/psychoreg.h#5 (text+ko) ==== @@ -28,7 +28,7 @@ * * from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp * - * $FreeBSD: src/sys/sparc64/pci/psychoreg.h,v 1.14 2007/09/06 19:16:30 marius Exp $ + * $FreeBSD: src/sys/sparc64/pci/psychoreg.h,v 1.15 2008/09/18 19:45:22 marius Exp $ */ #ifndef _SPARC64_PCI_PSYCHOREG_H_ @@ -265,10 +265,6 @@ #define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read */ #define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access */ -#define CEAFSR_ERRMASK \ - (CEAFSR_P_PIO | CEAFSR_P_DRD | CEAFSR_P_DWR | \ - CEAFSR_S_PIO | CEAFSR_S_DRD | CEAFSR_S_DWR) - /* PCI asynchronous fault status register */ #define PCIAFSR_P_MA (1UL << 63) /* Pri. master abort */ #define PCIAFSR_P_TA (1UL << 62) /* Pri. target abort */ @@ -282,10 +278,6 @@ #define PCIAFSR_BLK (1UL << 31) /* failed pri. transfer was block r/w */ #define PCIAFSR_MID (0x3eUL << 25) /* UPA MID causing error transaction */ -#define PCIAFSR_ERRMASK \ - (PCIAFSR_P_MA | PCIAFSR_P_TA | PCIAFSR_P_RTRY | PCIAFSR_P_RERR |\ - PCIAFSR_S_MA | PCIAFSR_S_TA | PCIAFSR_S_RTRY | PCIAFSR_S_RERR) - /* PCI diagnostic register */ #define DIAG_RTRY_DIS 0x0000000000000040 /* dis. retry limit */ #define DIAG_ISYNC_DIS 0x0000000000000020 /* dis. DMA write / int sync */
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