Date: Wed, 28 Nov 2018 06:54:25 +0000 (UTC) From: Andrew Rybchenko <arybchik@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341109 - head/sys/dev/sfxge/common Message-ID: <201811280654.wAS6sPAa083998@repo.freebsd.org>
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Author: arybchik Date: Wed Nov 28 06:54:25 2018 New Revision: 341109 URL: https://svnweb.freebsd.org/changeset/base/341109 Log: sfxge(4): move PF/VF config to ef10 NIC board config Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18185 Modified: head/sys/dev/sfxge/common/ef10_nic.c head/sys/dev/sfxge/common/hunt_nic.c head/sys/dev/sfxge/common/medford2_nic.c (contents, props changed) head/sys/dev/sfxge/common/medford_nic.c Modified: head/sys/dev/sfxge/common/ef10_nic.c ============================================================================== --- head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:54:13 2018 (r341108) +++ head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:54:25 2018 (r341109) @@ -1576,6 +1576,8 @@ ef10_nic_board_cfg( efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t port; + uint32_t pf; + uint32_t vf; efx_rc_t rc; /* Get the (zero-based) MCDI port number */ @@ -1589,13 +1591,27 @@ ef10_nic_board_cfg( &encp->enc_external_port)) != 0) goto fail2; + /* + * Get PCIe function number from firmware (used for + * per-function privilege and dynamic config info). + * - PCIe PF: pf = PF number, vf = 0xffff. + * - PCIe VF: pf = parent PF, vf = VF number. + */ + if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) + goto fail3; + + encp->enc_pf = pf; + encp->enc_vf = vf; + /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) if (rc != EACCES) - goto fail3; + goto fail4; return (0); +fail4: + EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: Modified: head/sys/dev/sfxge/common/hunt_nic.c ============================================================================== --- head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:54:13 2018 (r341108) +++ head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:54:25 2018 (r341109) @@ -108,8 +108,6 @@ hunt_board_cfg( uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t pf; - uint32_t vf; uint32_t mask; uint32_t flags; uint32_t sysclk, dpcpu_clk; @@ -127,18 +125,6 @@ hunt_board_cfg( EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - /* - * Get PCIe function number from firmware (used for - * per-function privilege and dynamic config info). - * - PCIe PF: pf = PF number, vf = 0xffff. - * - PCIe VF: pf = parent PF, vf = VF number. - */ - if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) - goto fail1; - - encp->enc_pf = pf; - encp->enc_vf = vf; - /* MAC address for this function */ if (EFX_PCI_FUNCTION_IS_PF(encp)) { rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); @@ -155,7 +141,7 @@ hunt_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail2; + goto fail1; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); @@ -166,7 +152,7 @@ hunt_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail3; + goto fail2; } encp->enc_board_type = board_type; @@ -174,11 +160,11 @@ hunt_board_cfg( /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail4; + goto fail3; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail5; + goto fail4; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -209,7 +195,7 @@ hunt_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug35388_workaround = B_FALSE; else - goto fail6; + goto fail5; /* * If the bug41750 workaround is enabled, then do not test interrupts, @@ -228,7 +214,7 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug41750_workaround = B_FALSE; } else { - goto fail7; + goto fail6; } if (EFX_PCI_FUNCTION_IS_VF(encp)) { /* Interrupt testing does not work for VFs. See bug50084. */ @@ -266,12 +252,12 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug26807_workaround = B_FALSE; } else { - goto fail8; + goto fail7; } /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail9; + goto fail8; /* * The Huntington timer quantum is 1536 sysclk cycles, documented for @@ -290,7 +276,7 @@ hunt_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail10; + goto fail9; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -340,13 +326,13 @@ hunt_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail11; + goto fail10; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail12; + goto fail11; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -362,7 +348,7 @@ hunt_board_cfg( encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) - goto fail13; + goto fail12; encp->enc_required_pcie_bandwidth_mbps = bandwidth; /* All Huntington devices have a PCIe Gen3, 8 lane connector */ @@ -370,8 +356,6 @@ hunt_board_cfg( return (0); -fail13: - EFSYS_PROBE(fail13); fail12: EFSYS_PROBE(fail12); fail11: Modified: head/sys/dev/sfxge/common/medford2_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:54:13 2018 (r341108) +++ head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:54:25 2018 (r341109) @@ -82,8 +82,6 @@ medford2_board_cfg( uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t pf; - uint32_t vf; uint32_t mask; uint32_t sysclk, dpcpu_clk; uint32_t base, nvec; @@ -105,18 +103,6 @@ medford2_board_cfg( encp->enc_vi_window_shift = vi_window_shift; - /* - * Get PCIe function number from firmware (used for - * per-function privilege and dynamic config info). - * - PCIe PF: pf = PF number, vf = 0xffff. - * - PCIe VF: pf = parent PF, vf = VF number. - */ - if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) - goto fail2; - - encp->enc_pf = pf; - encp->enc_vf = vf; - /* MAC address for this function */ if (EFX_PCI_FUNCTION_IS_PF(encp)) { rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); @@ -141,7 +127,7 @@ medford2_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail3; + goto fail2; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); @@ -152,7 +138,7 @@ medford2_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail4; + goto fail3; } encp->enc_board_type = board_type; @@ -160,11 +146,11 @@ medford2_board_cfg( /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail5; + goto fail4; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail6; + goto fail5; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -208,11 +194,11 @@ medford2_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug61265_workaround = B_FALSE; else - goto fail7; + goto fail6; /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail8; + goto fail7; /* * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for @@ -224,7 +210,7 @@ medford2_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail9; + goto fail8; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -232,7 +218,7 @@ medford2_board_cfg( /* Get the RX DMA end padding alignment configuration */ if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { if (rc != EACCES) - goto fail10; + goto fail9; /* Assume largest tail padding size supported by hardware */ end_padding = 256; @@ -284,13 +270,13 @@ medford2_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail11; + goto fail10; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail12; + goto fail11; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -313,14 +299,12 @@ medford2_board_cfg( rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth); if (rc != 0) - goto fail13; + goto fail12; encp->enc_required_pcie_bandwidth_mbps = bandwidth; encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; return (0); -fail13: - EFSYS_PROBE(fail13); fail12: EFSYS_PROBE(fail12); fail11: Modified: head/sys/dev/sfxge/common/medford_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:54:13 2018 (r341108) +++ head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:54:25 2018 (r341109) @@ -78,8 +78,6 @@ medford_board_cfg( uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t pf; - uint32_t vf; uint32_t mask; uint32_t sysclk, dpcpu_clk; uint32_t base, nvec; @@ -102,18 +100,6 @@ medford_board_cfg( EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - /* - * Get PCIe function number from firmware (used for - * per-function privilege and dynamic config info). - * - PCIe PF: pf = PF number, vf = 0xffff. - * - PCIe VF: pf = parent PF, vf = VF number. - */ - if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) - goto fail1; - - encp->enc_pf = pf; - encp->enc_vf = vf; - /* MAC address for this function */ if (EFX_PCI_FUNCTION_IS_PF(encp)) { rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); @@ -138,7 +124,7 @@ medford_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail2; + goto fail1; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); @@ -149,7 +135,7 @@ medford_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail3; + goto fail2; } encp->enc_board_type = board_type; @@ -157,11 +143,11 @@ medford_board_cfg( /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail4; + goto fail3; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail5; + goto fail4; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -205,11 +191,11 @@ medford_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug61265_workaround = B_FALSE; else - goto fail6; + goto fail5; /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail7; + goto fail6; /* * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for @@ -221,7 +207,7 @@ medford_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail8; + goto fail7; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -229,7 +215,7 @@ medford_board_cfg( /* Get the RX DMA end padding alignment configuration */ if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { if (rc != EACCES) - goto fail9; + goto fail8; /* Assume largest tail padding size supported by hardware */ end_padding = 256; @@ -281,13 +267,13 @@ medford_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail10; + goto fail9; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail11; + goto fail10; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -310,14 +296,12 @@ medford_board_cfg( rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth); if (rc != 0) - goto fail12; + goto fail11; encp->enc_required_pcie_bandwidth_mbps = bandwidth; encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; return (0); -fail12: - EFSYS_PROBE(fail12); fail11: EFSYS_PROBE(fail11); fail10:
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