Date: Mon, 14 Jul 1997 17:11:13 -0600 From: Steve Passe <smp@csn.net> To: Bob Bishop <rb@gid.co.uk> Cc: hackers@FreeBSD.ORG, smp@FreeBSD.ORG Subject: Re: interrupt latency Message-ID: <199707142311.RAA01616@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Mon, 14 Jul 1997 23:26:41 BST." <l0302090caff057b0d7a9@[194.32.164.2]>
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Hi, > >> A digital output port and an oscilloscope, logic analyser or something > >> similar. Any other (ie non-hardware) method is just inviting confusion. > [...] > >... and the 4th > >CPU could service the real INTs almost as fast as they occur. > ^^^^^^ > |||||| > > As I was saying... :-) but for this scheme that delay is irrelevant, as I can time exactly the difference from the point that the '4th CPU' sends the INT via the APIC bus and the time the ISR is completed. think of the 4th CPU as a very intelligent IO APIC that can record (once tied to specific software) all the timings of the INT events. -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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