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Date:      Wed, 28 Nov 2018 06:55:12 +0000 (UTC)
From:      Andrew Rybchenko <arybchik@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r341113 - head/sys/dev/sfxge/common
Message-ID:  <201811280655.wAS6tCM8084282@repo.freebsd.org>

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Author: arybchik
Date: Wed Nov 28 06:55:12 2018
New Revision: 341113
URL: https://svnweb.freebsd.org/changeset/base/341113

Log:
  sfxge(4): move datapath config to ef10 NIC board cfg
  
  Submitted by:   Andy Moreton <amoreton at solarflare.com>
  Sponsored by:   Solarflare Communications, Inc.
  Differential Revision:  https://reviews.freebsd.org/D18189

Modified:
  head/sys/dev/sfxge/common/ef10_impl.h
  head/sys/dev/sfxge/common/ef10_nic.c
  head/sys/dev/sfxge/common/hunt_nic.c
  head/sys/dev/sfxge/common/medford2_nic.c   (contents, props changed)
  head/sys/dev/sfxge/common/medford_nic.c

Modified: head/sys/dev/sfxge/common/ef10_impl.h
==============================================================================
--- head/sys/dev/sfxge/common/ef10_impl.h	Wed Nov 28 06:55:00 2018	(r341112)
+++ head/sys/dev/sfxge/common/ef10_impl.h	Wed Nov 28 06:55:12 2018	(r341113)
@@ -1188,10 +1188,6 @@ efx_mcdi_get_vector_cfg(
 	__out_opt	uint32_t *vf_nvecp);
 
 extern	__checkReturn	efx_rc_t
-ef10_get_datapath_caps(
-	__in		efx_nic_t *enp);
-
-extern	__checkReturn	efx_rc_t
 ef10_get_vi_window_shift(
 	__in		efx_nic_t *enp,
 	__out		uint32_t *vi_window_shiftp);

Modified: head/sys/dev/sfxge/common/ef10_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/ef10_nic.c	Wed Nov 28 06:55:00 2018	(r341112)
+++ head/sys/dev/sfxge/common/ef10_nic.c	Wed Nov 28 06:55:12 2018	(r341113)
@@ -1016,7 +1016,7 @@ fail1:
 	return (rc);
 }
 
-	__checkReturn	efx_rc_t
+static	__checkReturn	efx_rc_t
 ef10_get_datapath_caps(
 	__in		efx_nic_t *enp)
 {
@@ -1658,13 +1658,19 @@ ef10_nic_board_cfg(
 	epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
 	epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
+	/* Check capabilities of running datapath firmware */
+	if ((rc = ef10_get_datapath_caps(enp)) != 0)
+		goto fail8;
+
 	/* Get remaining controller-specific board config */
 	if ((rc = enop->eno_board_cfg(enp)) != 0)
 		if (rc != EACCES)
-			goto fail8;
+			goto fail9;
 
 	return (0);
 
+fail9:
+	EFSYS_PROBE(fail9);
 fail8:
 	EFSYS_PROBE(fail8);
 fail7:

Modified: head/sys/dev/sfxge/common/hunt_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/hunt_nic.c	Wed Nov 28 06:55:00 2018	(r341112)
+++ head/sys/dev/sfxge/common/hunt_nic.c	Wed Nov 28 06:55:12 2018	(r341113)
@@ -228,10 +228,6 @@ hunt_board_cfg(
 
 	encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
 
-	/* Check capabilities of running datapath firmware */
-	if ((rc = ef10_get_datapath_caps(enp)) != 0)
-		goto fail5;
-
 	/* Alignment for receive packet DMA buffers */
 	encp->enc_rx_buf_align_start = 1;
 	encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
@@ -280,13 +276,13 @@ hunt_board_cfg(
 	 * can result in time-of-check/time-of-use bugs.
 	 */
 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-		goto fail6;
+		goto fail5;
 	encp->enc_privilege_mask = mask;
 
 	/* Get interrupt vector limits */
 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
 		if (EFX_PCI_FUNCTION_IS_PF(encp))
-			goto fail7;
+			goto fail6;
 
 		/* Ignore error (cannot query vector limits from a VF). */
 		base = 0;
@@ -302,7 +298,7 @@ hunt_board_cfg(
 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
 	if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-		goto fail8;
+		goto fail7;
 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
 	/* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -310,8 +306,6 @@ hunt_board_cfg(
 
 	return (0);
 
-fail8:
-	EFSYS_PROBE(fail8);
 fail7:
 	EFSYS_PROBE(fail7);
 fail6:

Modified: head/sys/dev/sfxge/common/medford2_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford2_nic.c	Wed Nov 28 06:55:00 2018	(r341112)
+++ head/sys/dev/sfxge/common/medford2_nic.c	Wed Nov 28 06:55:12 2018	(r341113)
@@ -153,17 +153,13 @@ medford2_board_cfg(
 	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
-	/* Check capabilities of running datapath firmware */
-	if ((rc = ef10_get_datapath_caps(enp)) != 0)
-		goto fail4;
-
 	/* Alignment for receive packet DMA buffers */
 	encp->enc_rx_buf_align_start = 1;
 
 	/* Get the RX DMA end padding alignment configuration */
 	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
 		if (rc != EACCES)
-			goto fail5;
+			goto fail4;
 
 		/* Assume largest tail padding size supported by hardware */
 		end_padding = 256;
@@ -215,13 +211,13 @@ medford2_board_cfg(
 	 * can result in time-of-check/time-of-use bugs.
 	 */
 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-		goto fail6;
+		goto fail5;
 	encp->enc_privilege_mask = mask;
 
 	/* Get interrupt vector limits */
 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
 		if (EFX_PCI_FUNCTION_IS_PF(encp))
-			goto fail7;
+			goto fail6;
 
 		/* Ignore error (cannot query vector limits from a VF). */
 		base = 0;
@@ -244,14 +240,12 @@ medford2_board_cfg(
 
 	rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
 	if (rc != 0)
-		goto fail8;
+		goto fail7;
 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
 	return (0);
 
-fail8:
-	EFSYS_PROBE(fail8);
 fail7:
 	EFSYS_PROBE(fail7);
 fail6:

Modified: head/sys/dev/sfxge/common/medford_nic.c
==============================================================================
--- head/sys/dev/sfxge/common/medford_nic.c	Wed Nov 28 06:55:00 2018	(r341112)
+++ head/sys/dev/sfxge/common/medford_nic.c	Wed Nov 28 06:55:12 2018	(r341113)
@@ -150,17 +150,13 @@ medford_board_cfg(
 	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
-	/* Check capabilities of running datapath firmware */
-	if ((rc = ef10_get_datapath_caps(enp)) != 0)
-		goto fail3;
-
 	/* Alignment for receive packet DMA buffers */
 	encp->enc_rx_buf_align_start = 1;
 
 	/* Get the RX DMA end padding alignment configuration */
 	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
 		if (rc != EACCES)
-			goto fail4;
+			goto fail3;
 
 		/* Assume largest tail padding size supported by hardware */
 		end_padding = 256;
@@ -212,13 +208,13 @@ medford_board_cfg(
 	 * can result in time-of-check/time-of-use bugs.
 	 */
 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-		goto fail5;
+		goto fail4;
 	encp->enc_privilege_mask = mask;
 
 	/* Get interrupt vector limits */
 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
 		if (EFX_PCI_FUNCTION_IS_PF(encp))
-			goto fail6;
+			goto fail5;
 
 		/* Ignore error (cannot query vector limits from a VF). */
 		base = 0;
@@ -241,14 +237,12 @@ medford_board_cfg(
 
 	rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
 	if (rc != 0)
-		goto fail7;
+		goto fail6;
 	encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 	encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
 	return (0);
 
-fail7:
-	EFSYS_PROBE(fail7);
 fail6:
 	EFSYS_PROBE(fail6);
 fail5:



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