Date: Sun, 16 Nov 2014 20:34:14 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r274596 - head/sys/arm/arm Message-ID: <201411162034.sAGKYEwt088653@svn.freebsd.org>
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Author: ian Date: Sun Nov 16 20:34:14 2014 New Revision: 274596 URL: https://svnweb.freebsd.org/changeset/base/274596 Log: Indent a couple lines properly and expand a comment. No functional changes. Modified: head/sys/arm/arm/busdma_machdep-v6.c Modified: head/sys/arm/arm/busdma_machdep-v6.c ============================================================================== --- head/sys/arm/arm/busdma_machdep-v6.c Sun Nov 16 20:29:57 2014 (r274595) +++ head/sys/arm/arm/busdma_machdep-v6.c Sun Nov 16 20:34:14 2014 (r274596) @@ -1336,7 +1336,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus (void *)bpage->vaddr, bpage->datacount); cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, - bpage->datacount); + bpage->datacount); l2cache_wb_range((vm_offset_t)bpage->vaddr, (vm_offset_t)bpage->busaddr, bpage->datacount); @@ -1390,12 +1390,16 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus /* * For COHERENT memory no cache maintenance is necessary, but ensure all - * writes have reached memory for the PREWRITE case. + * writes have reached memory for the PREWRITE case. No action is + * needed for a PREREAD without PREWRITE also set, because that would + * imply that the cpu had written to the COHERENT buffer and expected + * the dma device to see that change, and by definition a PREWRITE sync + * is required to make that happen. */ if (map->flags & DMAMAP_COHERENT) { if (op & BUS_DMASYNC_PREWRITE) { - dsb(); - cpu_l2cache_drain_writebuf(); + dsb(); + cpu_l2cache_drain_writebuf(); } return; }
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