Date: Mon, 22 Mar 1999 12:45:21 -0800 (PST) From: Matthew Dillon <dillon@apollo.backplane.com> To: Dennis <dennis@etinc.com> Cc: Mike Smith <mike@smith.net.au>, Amancio Hasty <hasty@rah.star-gate.com>, hackers@FreeBSD.ORG Subject: Re: Gigabit ethernet -- what am I doing wrong? Message-ID: <199903222045.MAA24353@apollo.backplane.com> References: <Your message of "Sun, 21 Mar 1999 20:10:21 EST." <199903220058.TAA17538@etinc.com> <199903221711.MAA20551@etinc.com> <199903222019.PAA21360@etinc.com>
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:>:Dennis
:>
:> All PCI card chipsets implement internal read and write
:> DMA FIFO's. Thus a 64 bit PCI card can easily burst 64 bit
:> words over the PCI bus. If the processor on the card
:> itself cannot stuff the FIFO quickly enough to hold the burst
:> for a period longer then the size of the FIFO, it's no big deal
:> because the processor on the card can obviously pump data
:> sufficiently to handle the physical I/O it is supporting for
:> that card , and the FIFO is large enough such that the
:> shorter higher-speed burst on the PCI bus will be sufficient
:> enough to use the PCI bus bandwidth efficiently. What bandwidth
:> cannot be used by one card will certainly be used by another.
:>
:> This just isn't an issue.
:Shorter bursts are less efficient, which implies that 64bit PCI transfers
:can be not much better than 32bit with sustained bursts, which is
:my point. You could easily have a 64-bit pci card that was slower than
:(or the same as) a 32-bit one due to this factor. Im not arguing that it
:doesnt work, only that its not a cureall to the throughput problem.
:
:Dennis
Dennis, please read my response more carefully and you will understand
why your concerns are unfounded. I will paraphrase: "The FIFOs are
large enough such that the burst is going to be relatively efficient
no matter what the PCI bus width and no matter how slow the card".
The problem that is being solved here is not a card's ability to sustain
a long burst, but instead the bandwidth available on the PCI bus when
multiple cards are operating. There is no advantage to any single card
being able to do long sustained bursts on a faster PCI bus because they
are already limited to the speed physical media they were built to handle.
The requirement is for the card to be able to sustain a reasonably-sized
burst so the PCI bus's transactional overhead remains small verses the
actual data transfer. This is what the FIFO accomplishes.
-Matt
Matthew Dillon
<dillon@backplane.com>
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