Date: Thu, 14 Mar 2019 21:08:48 +0000 (UTC) From: Conrad Meyer <cem@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r345158 - head/usr.sbin/bhyve Message-ID: <201903142108.x2EL8mGv018392@repo.freebsd.org>
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Author: cem Date: Thu Mar 14 21:08:48 2019 New Revision: 345158 URL: https://svnweb.freebsd.org/changeset/base/345158 Log: bhyve(8): Fix uart emulation bug THRE is always asserted in LSR reads, so REG_IER writes that raise IER_ETXRDY must also set thre_int_pending. Reported by: Illumos, according to emaste@ https://twitter.com/ed_maste/status/1106195949087584258 MFC after: 2 weeks Modified: head/usr.sbin/bhyve/uart_emul.c Modified: head/usr.sbin/bhyve/uart_emul.c ============================================================================== --- head/usr.sbin/bhyve/uart_emul.c Thu Mar 14 20:32:48 2019 (r345157) +++ head/usr.sbin/bhyve/uart_emul.c Thu Mar 14 21:08:48 2019 (r345158) @@ -431,6 +431,9 @@ uart_write(struct uart_softc *sc, int offset, uint8_t sc->thre_int_pending = true; break; case REG_IER: + /* Set pending when IER_ETXRDY is raised (edge-triggered). */ + if ((sc->ier & IER_ETXRDY) == 0 && (value & IER_ETXRDY) != 0) + sc->thre_int_pending = true; /* * Apply mask so that bits 4-7 are 0 * Also enables bits 0-3 only if they're 1
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