Date: Sat, 25 Sep 2004 22:51:50 -0600 (MDT) From: "M. Warner Losh" <imp@bsdimp.com> To: PeterJeremy@optushome.com.au Cc: cvs-src@freebsd.org Subject: Re: cvs commit: src/sys/net if.c Message-ID: <20040925.225150.20525280.imp@bsdimp.com> In-Reply-To: <20040925203122.GF83620@cirb503493.alcatel.com.au> References: <20040924094950.N39925@pooker.samsco.org> <20040924161807.GJ959@green.homeunix.org> <20040925203122.GF83620@cirb503493.alcatel.com.au>
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In message: <20040925203122.GF83620@cirb503493.alcatel.com.au>
Peter Jeremy <PeterJeremy@optushome.com.au> writes:
: On Fri, 2004-Sep-24 12:18:07 -0400, Brian Fundakowski Feldman wrote:
: >On Fri, Sep 24, 2004 at 09:51:31AM -0600, Scott Long wrote:
: >> On Fri, 24 Sep 2004, Brian Fundakowski Feldman wrote:
: >> > Every time it "appears" to be fixed, I can't get any kind of stability
: >> > with SMP, PREEMPTION, and SCHED_ULE; I'm certainly willing to try it
: >> > each time it looks to be fixed.
: >>
: >> Would you please copy me on the reports that you've sent to Julian so I
: >> can track them also?
: >
: >The only way I can get reports other than "it hung, serial DDB and
: >SW_WATCHDOG are no help" is if somehow I gain some kind of real
: >hardware watchdog. :(
:
: If you have an ISA slot handy, you can trivially generate NMI by
: shorting a pair of opposite pins (from memory the pair closest to the
: rear but I can't quickly verify that). Unfortunately, raising SERR#
: on a PCI bus appears to require some logic.
A1 and B1 pins. This clocks #IOCHK. However, this doesn't work on
all bridge chipsets, and many of them don't reset correctly w/o
changes to the tree. I've submitted them to bde a long time ago, but
he didn't like them for reasons that I don't recall at the moment.
However, it will work on most chipsets.
Warner
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