Date: Mon, 15 Jul 2013 20:39:50 GMT From: Brooks Davis <brooks@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 231181 for review Message-ID: <201307152039.r6FKdoZ0039478@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@231181?ac=10 Change 231181 by brooks@brooks_zenith on 2013/07/15 20:39:26 Sync with FreeBSD/BERI. Pulls in recent SMP work. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/boot/fdt/dts/beri-sim.dts#3 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/boot/fdt/dts/beripad-de4.dts#12 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/conf/options#9 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/conf/options.mips#11 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/dev/altera/sdcard/altera_sdcard.c#5 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/beri_mp.c#3 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/beri_pic.c#5 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/std.beri#6 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cavium/octeon_mp.c#4 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/conf/BERI_SIM_BASE#2 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/conf/BERI_SIM_MDROOT#8 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/gxemul/gxemul_machdep.c#5 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/hwfunc.h#5 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/cache.c#4 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/cpu.c#5 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/mp_machdep.c#4 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/nlm/xlp_machdep.c#4 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/rmi/xlr_machdep.c#4 integrate .. //depot/projects/ctsrd/cheribsd/src/sys/mips/sibyte/sb_machdep.c#5 integrate Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/boot/fdt/dts/beri-sim.dts#3 (text+ko) ==== @@ -47,9 +47,34 @@ #size-cells = <1>; cpus { + #address-cells = <1>; + #size-cells = <1>; + + /* + * Secondary CPUs all start disabled and use the + * spin-table enable method. cpu-release-addr must be + * specified for each cpu other than cpu@0. Values of + * cpu-release-addr grow down from 0x100000 (kernel). + */ + status = "disabled"; + enable-method = "spin-table"; + cpu@0 { + device-type = "cpu"; compatible = "sri-cambridge,beri"; + + reg = <0>; + status = "okay"; }; + + cpu@1 { + device-type = "cpu"; + compatible = "sri-cambridge,beri"; + + reg = <1>; + // XXX: should we need cached prefix? + cpu-release-addr = <0xffffffff 0x800fffe0>; + }; }; soc { @@ -69,10 +94,24 @@ reg = <0x0 0x4000000>; // 64M at 0x0 }; + beripic: beripic@7f804000 { + compatible = "sri-cambridge,beri-pic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg= <0x7f804000 0x400 + 0x7f806000 0x10 + 0x7f806080 0x10 + 0x7f806100 0x10>; + interrupts = <0 1 2 3 4>; + hard-interrupt-sources = <64>; + soft-interrupt-sources = <64>; + }; + serial@7f000000 { compatible = "altera,jtag_uart-11_0"; reg = <0x7f000000 0x40>; - interrupts = <0>; + //interrupts = <0>; }; serial@7f001000 { ==== //depot/projects/ctsrd/cheribsd/src/sys/boot/fdt/dts/beripad-de4.dts#12 (text+ko) ==== @@ -67,6 +67,15 @@ reg = <0>; status = "okay"; }; + + cpu@1 { + device-type = "cpu"; + compatible = "sri-cambridge,beri"; + + reg = <1>; + // XXX: should we need cached prefix? + cpu-release-addr = <0xffffffff 0x800fffe0>; + } }; soc { @@ -183,26 +192,26 @@ ethernet@7f007000 { compatible = "altera,atse"; - /* MAC, RX+RXC, TX+TXC. */ + // MAC, RX+RXC, TX+TXC. reg = <0x7f007000 0x400 0x7f007500 0x8 0x7f007520 0x20 0x7f007400 0x8 0x7f007420 0x20>; - /* RX, TX */ + // RX, TX interrupts = <1 2>; interrupt-parent = <&beripic>; }; ethernet@7f005000 { compatible = "altera,atse"; - /* MAC, RX+RXC, TX+TXC. */ + // MAC, RX+RXC, TX+TXC. reg = <0x7f005000 0x400 0x7f005500 0x8 0x7f005520 0x20 0x7f005400 0x8 0x7f005420 0x20>; - /* RX, TX */ + // RX, TX interrupts = <11 12>; interrupt-parent = <&beripic>; }; @@ -221,7 +230,6 @@ 0x7f006100 0x007f>; }; -/* usb@0x7f100000 { compatible = "philips,isp1761"; reg = <0x7f100000 0x40000 @@ -230,7 +238,6 @@ interrupts = <4 5>; interrupt-parent = <&beripic>; }; -*/ avgen@0x7f009000 { compatible = "sri-cambridge,avgen"; ==== //depot/projects/ctsrd/cheribsd/src/sys/conf/options#9 (text+ko) ==== @@ -68,6 +68,7 @@ # Miscellaneous options. ADAPTIVE_LOCKMGRS ALQ +ALTERA_SDCARD_FAST_SIM opt_altera_sdcard.h AUDIT opt_global.h BOOTHOWTO opt_global.h BOOTVERBOSE opt_global.h ==== //depot/projects/ctsrd/cheribsd/src/sys/conf/options.mips#11 (text+ko) ==== @@ -70,6 +70,11 @@ MAXMEM opt_global.h # +# Manual override of cache config +# +MIPS_DISABLE_L1_CACHE opt_global.h + +# # Options that control the Cavium Simple Executive. # OCTEON_MODEL opt_cvmx.h ==== //depot/projects/ctsrd/cheribsd/src/sys/dev/altera/sdcard/altera_sdcard.c#5 (text+ko) ==== @@ -31,6 +31,8 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD: head/sys/dev/altera/sdcard/altera_sdcard.c 245380 2013-01-13 16:57:11Z rwatson $"); +#include "opt_altera_sdcard.h" + #include <sys/param.h> #include <sys/bus.h> #include <sys/condvar.h> @@ -258,6 +260,9 @@ ALTERA_SDCARD_LOCK_ASSERT(sc); KASSERT(sc->as_currentbio != NULL, ("%s: no current I/O", __func__)); +#ifdef ALTERA_SDCARD_FAST_SIM +recheck: +#endif asr = altera_sdcard_read_asr(sc); /* @@ -299,9 +304,12 @@ /* * Finally, either start the next I/O or transition to the IDLE state. */ - if (bioq_first(&sc->as_bioq) != NULL) + if (bioq_first(&sc->as_bioq) != NULL) { altera_sdcard_nextio(sc); - else +#ifdef ALTERA_SDCARD_FAST_SIM + goto recheck; +#endif + } else sc->as_state = ALTERA_SDCARD_STATE_IDLE; } @@ -398,6 +406,8 @@ taskqueue_cancel_timeout(sc->as_taskqueue, &sc->as_task, NULL); altera_sdcard_nextio(sc); - taskqueue_enqueue_timeout(sc->as_taskqueue, &sc->as_task, - ALTERA_SDCARD_TIMEOUT_IO); +#ifdef ALTERA_SDCARD_FAST_SIM + altera_sdcard_task_io(sc); +#endif + altera_sdcard_task_rechedule(sc); } ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/beri_mp.c#3 (text+ko) ==== @@ -57,6 +57,8 @@ { phandle_t cpus, cpu; pcell_t reg; + char prop[16]; + struct spin_entry *se; if ((cpus = OF_finddevice("/cpus")) <= 0) { printf("%s: no \"/cpus\" device found in FDT\n", __func__); @@ -76,8 +78,36 @@ if (reg > MAXCPU) { printf("%s: cpu ID too large (%d > %d)\n", __func__, reg, MAXCPU); + continue; } cpu_of_nodes[reg] = cpu; + + if (reg != 0) { + if (OF_getprop(cpu, "enable-method", &prop, + sizeof(prop)) <= 0 && OF_getprop(OF_parent(cpu), + "enable-method", &prop, sizeof(prop)) <= 0) { + printf("%s: CPU %d has no enable-method " + "property\n", __func__, reg); + continue; + } + if (strcmp("spin-table", prop) != 0) { + printf("%s: CPU %d enable-method is '%s' not " + "'spin-table'\n", __func__, reg, prop); + continue; + } + + if (OF_getprop(cpu, "cpu-release-addr", &se, + sizeof(se)) <= 0) { + printf("%s: CPU %d has missing or invalid " + "cpu-release-addr\n", __func__, reg); + continue; + } + if (se->entry_addr != 1) { + printf("%s: CPU %d has uninitalized spin " + "entry\n", __func__, reg); + continue; + } + } CPU_SET(reg, mask); } while ((cpu = OF_peer(cpu)) > 0); @@ -91,10 +121,29 @@ * XXX: panic instead? */ CPU_ZERO(mask); - CPU_SET(1, mask); + CPU_SET(0, mask); } void +platform_init_secondary(int cpuid) +{ + device_t ic; + int ipi; + + ipi = platform_ipi_intrnum(); + + /* XXX: single core/pic */ + ic = SLIST_FIRST(&fdt_ic_list_head)->dev; + FDT_IC_SETUP_IPI(ic, cpuid, ipi); + picmap[cpuid] = ic; + + /* Unmask the interrupt */ + if (cpuid != 0) + mips_wr_status(mips_rd_status() | (((1 << ipi) << 8) << 2)); +} + + +void platform_ipi_send(int cpuid) { @@ -135,7 +184,6 @@ platform_init_ap(int cpuid) { u_int clock_int_mask; - device_t ic; KASSERT(cpuid < MAXCPU, ("%s: invalid CPU id %d", __func__, cpuid)); @@ -144,14 +192,6 @@ */ clock_int_mask = hard_int_mask(5); set_intr_mask(clock_int_mask); - - /* - * Enable IPIs. - */ - /* XXX: single core/pic */ - ic = SLIST_FIRST(&fdt_ic_list_head)->dev; - FDT_IC_SETUP_IPI(ic, cpuid, platform_ipi_intrnum()); - picmap[cpuid] = ic; } /* @@ -171,22 +211,31 @@ ("%s: invalid CPU id %d", __func__, cpuid)); cpu = cpu_of_nodes[cpuid]; - if (OF_getprop(cpu, "status", &prop, sizeof(prop)) <= 0 && - OF_getprop(OF_parent(cpu), "status", &prop, sizeof(prop))) - panic("%s: CPU %d has no status property", __func__, cpuid); - else - if (strcmp("disabled", prop) != 0) - panic("%s: CPU %d status is '%s' not 'disabled'", - __func__, cpuid, prop); + if (OF_getprop(cpu, "status", &prop, sizeof(prop)) <= 0) { + if (bootverbose) + printf("%s: CPU %d has no status property, " + "trying parent\n", __func__, cpuid); + if (OF_getprop(OF_parent(cpu), "status", &prop, + sizeof(prop)) <= 0) + panic("%s: CPU %d has no status property", __func__, + cpuid); + } + if (strcmp("disabled", prop) != 0) + panic("%s: CPU %d status is '%s' not 'disabled'", + __func__, cpuid, prop); - if (OF_getprop(cpu, "enable-method", &prop, sizeof(prop)) <= 0 && - OF_getprop(OF_parent(cpu), "enable-method", &prop, sizeof(prop))) - panic("%s: CPU %d has no enable-method property", __func__, - cpuid); - else - if (strcmp("spin-table", prop) != 0) - panic("%s: CPU %d enable-method is '%s' not " - "'spin-table'", __func__, cpuid, prop); + if (OF_getprop(cpu, "enable-method", &prop, sizeof(prop)) <= 0) { + if (bootverbose) + printf("%s: CPU %d has no enable-method, " + "trying parent\n", __func__, cpuid); + if (OF_getprop(OF_parent(cpu), "enable-method", &prop, + sizeof(prop)) <= 0) + panic("%s: CPU %d has no enable-method property", + __func__, cpuid); + } + if (strcmp("spin-table", prop) != 0) + panic("%s: CPU %d enable-method is '%s' not " + "'spin-table'", __func__, cpuid, prop); if (OF_getprop(cpu, "cpu-release-addr", &se, sizeof(se)) <= 0) panic("%s: CPU %d has missing or invalid cpu-release-addr", ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/beri_pic.c#5 (text+ko) ==== @@ -218,7 +218,9 @@ static void bp_config_source(device_t ic, int src, int enable, u_long tid, u_long irq) { +#if 0 char configstr[64]; +#endif struct beripic_softc *sc; uint64_t config; @@ -229,9 +231,12 @@ config |= tid << BP_CFG_SHIFT_TID; config |= irq << BP_CFG_SHIFT_IRQ; - if (bootverbose) +#if 0 + /* There is not valid console when doing IPI setup on APs */ + if (bootverbose && (tid == 0 || !cold)) device_printf(ic, "src %d: %s\n", src, bp_strconfig(config, configstr, sizeof(configstr))); +#endif bp_write_cfg(sc, src, config); } @@ -552,12 +557,14 @@ if (error != 0) goto err; +#ifdef NOTYET #ifdef SMP /* XXX: bind ithread to cpu */ sc->bp_next_tid++; if (sc->bp_next_tid >= sc->bp_nthreads) sc->bp_next_tid = 0; #endif +#endif if (sc->bp_next_tid == 0) { sc->bp_next_irq++; if (sc->bp_next_irq >= sc->bp_nirqs) @@ -650,7 +657,7 @@ bit = 1ULL << (tid % 64); bus_space_write_8(sc->bp_set_bst, sc->bp_set_bsh, - BP_FIRST_SOFT / 8 + (tid >> 6), bit); + (BP_FIRST_SOFT / 8) + (tid / 64), bit); } static void @@ -665,7 +672,7 @@ bit = 1ULL << (tid % 64); bus_space_write_8(sc->bp_clear_bst, sc->bp_clear_bsh, - BP_FIRST_SOFT / 8 + (tid >> 6), bit); + (BP_FIRST_SOFT / 8) + (tid / 64), bit); } #endif ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/beri/std.beri#6 (text+ko) ==== @@ -4,4 +4,4 @@ cpu CPU_MIPS4KC options BERI_LARGE_TLB - +options MIPS_DISABLE_L1_CACHE ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cavium/octeon_mp.c#4 (text+ko) ==== @@ -46,6 +46,12 @@ unsigned octeon_ap_boot = ~0; void +platform_init_secondary(int cpuid) +{ + +} + +void platform_ipi_send(int cpuid) { cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1); ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/conf/BERI_SIM_BASE#2 (text+ko) ==== @@ -12,6 +12,8 @@ options FDT_DTB_STATIC makeoptions FDT_DTS_FILE=beri-sim.dts +options ALTERA_SDCARD_FAST_SIM + device altera_avgen device altera_jtag_uart device altera_sdcard ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/conf/BERI_SIM_MDROOT#8 (text+ko) ==== @@ -10,9 +10,9 @@ ident BERI_SIM_MDROOT # -# This kernel configuration uses an embedded 8MB memory root file system. +# This kernel configuration uses an embedded memory root file system. # Adjust the following path based on local requirements. # options MD_ROOT # MD is a potential root device -options MD_ROOT_SIZE=8192 +options MD_ROOT_SIZE=26112 # 25.5MB options ROOTDEVNAME=\"ufs:md0\" ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/gxemul/gxemul_machdep.c#5 (text+ko) ==== @@ -174,6 +174,12 @@ #ifdef SMP void +platform_init_secondary(int cpuid) +{ + +} + +void platform_ipi_send(int cpuid) { GXEMUL_MP_DEV_WRITE(GXEMUL_MP_DEV_IPI_ONE, (1 << 16) | cpuid); ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/hwfunc.h#5 (text+ko) ==== @@ -70,6 +70,11 @@ int platform_ipi_intrnum(void); /* + * Set up IPIs for this CPU. + */ +void platform_init_secondary(int cpuid); + +/* * Trigger a IPI interrupt on 'cpuid'. */ void platform_ipi_send(int cpuid); ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/cache.c#4 (text+ko) ==== @@ -116,11 +116,9 @@ #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_icache_sync_all = cache_noop; - mips_cache_ops.mco_icache_sync_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_icache_sync_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop; + mips_cache_ops.mco_icache_sync_range = cache_noop; + mips_cache_ops.mco_icache_sync_range_index = cache_noop; break; #endif default: @@ -193,20 +191,16 @@ #endif #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = + mips_cache_ops.mco_intern_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_inv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; + mips_cache_ops.mco_pdcache_wb_range = cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; break; #endif default: @@ -222,26 +216,22 @@ #ifdef CACHE_DEBUG printf(" Dcache is coherent\n"); #endif - mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_inv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; + mips_cache_ops.mco_pdcache_wb_range = cache_noop; } if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { #ifdef CACHE_DEBUG printf(" Icache is coherent against Dcache\n"); #endif mips_cache_ops.mco_intern_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; } #endif ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/cpu.c#5 (text+ko) ==== @@ -128,6 +128,9 @@ #endif /* L1 instruction cache. */ +#ifdef MIPS_DISABLE_L1_CACHE + cpuinfo->l1.ic_linesize = 0; +#else tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; if (tmp != 0) { cpuinfo->l1.ic_linesize = 1 << (tmp + 1); @@ -135,9 +138,13 @@ cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); } +#endif + /* L1 data cache. */ +#ifdef MIPS_DISABLE_L1_CACHE + cpuinfo->l1.dc_linesize = 0; +#else #ifndef CPU_CNMIPS - /* L1 data cache. */ tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; if (tmp != 0) { cpuinfo->l1.dc_linesize = 1 << (tmp + 1); @@ -173,6 +180,7 @@ /* All Octeon models use 128 byte line size. */ cpuinfo->l1.dc_linesize = 128; #endif +#endif cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways; ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/mips/mp_machdep.c#4 (text+ko) ==== @@ -301,6 +301,8 @@ while (!aps_ready) ; + platform_init_secondary(cpuid); + /* Initialize curthread. */ KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); PCPU_SET(curthread, PCPU_GET(idlethread)); @@ -342,6 +344,8 @@ if (mp_ncpus == 1) return; + platform_init_secondary(0); + /* * IPI handler */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/nlm/xlp_machdep.c#4 (text+ko) ==== @@ -697,6 +697,12 @@ } void +platform_init_secondary(int cpuid) +{ + +} + +void platform_ipi_send(int cpuid) { ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/rmi/xlr_machdep.c#4 (text+ko) ==== @@ -578,6 +578,12 @@ } void +platform_init_secondary(int cpuid) +{ + +} + +void platform_ipi_send(int cpuid) { ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/sibyte/sb_machdep.c#5 (text+ko) ==== @@ -295,6 +295,12 @@ #ifdef SMP void +platform_init_secondary(int cpuid) +{ + +} + +void platform_ipi_send(int cpuid) { KASSERT(cpuid == 0 || cpuid == 1,
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