Date: Thu, 17 Jul 1997 15:57:59 +0800 From: Peter Wemm <peter@spinner.dialix.com.au> To: vanmaren@fast.cs.utah.edu (Kevin Van Maren) Cc: smp@FreeBSD.ORG, smp@csn.net Subject: Re: HEADS UP: EISA cards. Message-ID: <199707170757.PAA25690@spinner.dialix.com.au> In-Reply-To: Your message of "Wed, 16 Jul 1997 09:16:35 CST." <199707161516.JAA02892@fast.cs.utah.edu>
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Kevin Van Maren wrote: > Okay, I'll bite. > > First off, I think that you DO want to abandon the 8254 timer > under SMP. The APIC's internal timer is much nicer. Not necessarily. The 8254 timer has the advantage that it's global, and is calibrated at boot. The APIC timers are per cpu and are (apparently) implemented as memory bus devices on the silicon, so it's just the same as an off-chip non-cacheable access (hence the elimination of accesses to the APIC_ID register after boot). The APIC timer is currently used for timing the IPI state sequences, and appears to be ideally suited for the precise timing that it needs. We can't easily use the single APIC timer for IPI timing *and* the system clock at the same time. It might be nice to build a precision event system around it at some later point (can you say, high resolution realtime sleeps, select sleeps, etc), and use the elapsed time of the IPI interval in the "time to next event" arithmatic etc, but we've got bigger things to worry about until then. Cheers, -Peter
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