Date: Tue, 1 Sep 2020 01:57:59 +0000 (UTC) From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r547233 - head/cad/verilator Message-ID: <202009010157.0811vxP2099763@repo.freebsd.org>
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Author: yuri Date: Tue Sep 1 01:57:59 2020 New Revision: 547233 URL: https://svnweb.freebsd.org/changeset/ports/547233 Log: cad/verilator: Add the 'test' target Modified: head/cad/verilator/Makefile Modified: head/cad/verilator/Makefile ============================================================================== --- head/cad/verilator/Makefile Tue Sep 1 01:53:27 2020 (r547232) +++ head/cad/verilator/Makefile Tue Sep 1 01:57:59 2020 (r547233) @@ -14,10 +14,14 @@ COMMENT= Synthesizable Verilog to C++ compiler LICENSE= GPLv3 LICENSE_FILE= ${WRKSRC}/LICENSE -USES= bison compiler:c++14-lang gmake pathfix perl5 tar:tgz +USES= bison compiler:c++14-lang gmake pathfix perl5 python:test tar:tgz GNU_CONFIGURE= yes CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}" + +TEST_TARGET= test + +BINARY_ALIAS= make=${GMAKE} python3=${PYTHON_CMD} # aliasas are only for tests post-patch: ${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
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