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Date:      Sat, 15 Dec 2001 13:38:05 -0800
From:      Mike Haertel <mike@ducky.net>
To:        freebsd-ports@freebsd.org, kaveman@magna.com.au
Subject:   improvement for FreeBSD Spice port
Message-ID:  <200112152138.fBFLc5r75928@ducky.net>

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Here are patches for ports/cad/spice to incorporate the latest
BSIM3 MOS transistor model from Berkeley.  With this addition, I
have successfully used Berkeley Spice to simulate circuits in
a .13 micron process, obtaining nearly identical results with
hspice (a hideously expensive commercial version of spice).

Index: Makefile
===================================================================
RCS file: /home/ncvs/ports/cad/spice/Makefile,v
retrieving revision 1.18
diff -u -r1.18 Makefile
--- Makefile	14 Feb 2001 05:41:52 -0000	1.18
+++ Makefile	15 Dec 2001 21:27:35 -0000
@@ -6,11 +6,16 @@
 #
 
 PORTNAME=	spice
-PORTVERSION=	3f5.1
+PORTVERSION=	3f5.2
 CATEGORIES=	cad
-MASTER_SITES=	ftp://ic.eecs.berkeley.edu/pub/Spice3/
+MASTER_SITES=	ftp://ic.eecs.berkeley.edu/pub/Spice3/ \
+		http://www-device.eecs.berkeley.edu/~bsim3/ftpv323/src/
+DISTFILES=	${DISTNAME}${EXTRACT_SUFX} ${BSIM_SRC}
 DISTNAME=	sp3f4.kit
 EXTRACT_SUFX=	.tar.Z
+EXTRACT_ONLY=	${DISTNAME}${EXTRACT_SUFX}
+
+BSIM_SRC=	BSIM3v323.tar.Z
 
 MAINTAINER=	kaveman@magna.com.au
 
@@ -26,6 +31,11 @@
 MAN3=		mfb.3
 MAN5=		mfbcap.5
 MLINKS=		spice.1 spice3.1
+
+post-extract:
+	${ECHO_MSG} ">>> in post-extract ..."
+	${MKDIR} ${WRKDIR}/src/lib/dev/bsim3
+	${TAR} -C ${WRKDIR}/src/lib/dev/bsim3 -xzf ${DISTDIR}/${BSIM_SRC}
 
 post-install:
 .if !defined(NOPORTDOCS)
Index: distinfo
===================================================================
RCS file: /home/ncvs/ports/cad/spice/distinfo,v
retrieving revision 1.2
diff -u -r1.2 distinfo
--- distinfo	23 Dec 1996 07:26:18 -0000	1.2
+++ distinfo	30 Nov 2001 06:14:52 -0000
@@ -1 +1,2 @@
 MD5 (sp3f4.kit.tar.Z) = d55eb08a7f523248b1b509092a444aeb
+MD5 (BSIM3v323.tar.Z) = 5c6cfd0f9cff1bb7f75ca236ea9b4b41
Index: pkg-descr
===================================================================
RCS file: /home/ncvs/ports/cad/spice/pkg-descr,v
retrieving revision 1.5
diff -u -r1.5 pkg-descr
--- pkg-descr	2 May 1999 21:40:08 -0000	1.5
+++ pkg-descr	30 Nov 2001 06:54:06 -0000
@@ -15,3 +15,13 @@
 
 Julian Jenkins
 kaveman@magna.com.au
+
+This port now incorporates Berkeley's latest BSIM3 v3.2 MOS transistor
+model for deep submicron designs.  Many foundries provide process parameter
+files compatible with this model.  To access the BSIM3 model, use LEVEL=7
+and VERSION=3.2.3 in your .MODEL directives.
+ 
+http://www-device.eecs.berkeley.edu/~bsim3/
+ 
+Mike Haertel
+mike@ducky.net
Index: files/patch-bc
===================================================================
RCS file: files/patch-bc
diff -N files/patch-bc
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ files/patch-bc	30 Nov 2001 06:25:20 -0000
@@ -0,0 +1,19 @@
+--- conf/defaults.orig	Thu Nov 29 22:24:06 2001
++++ conf/defaults	Thu Nov 29 22:25:05 2001
+@@ -237,6 +237,7 @@
+ #		bjt:	bipolar junction transistor
+ #		bsim1:	MOS model
+ #		bsim2:	MOS model
++#		bsim3:	deep submicron MOS model
+ #		cap:	capacitor
+ #		cccs:	current-controlled current source
+ #		ccvs:	current-controlled voltage source
+@@ -259,7 +260,7 @@
+ #		vcvs:	voltage-controlled voltage source
+ #		vsrc:	voltage source
+ 
+-DEVICES		= asrc bjt bsim1 bsim2 cap cccs ccvs csw dio ind isrc \
++DEVICES		= asrc bjt bsim1 bsim2 bsim3 cap cccs ccvs csw dio ind isrc \
+ 		  jfet ltra mes mos1 mos2 mos3 mos6 res sw tra urc \
+ 		  vccs vcvs vsrc
+ 

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