Date: Mon, 5 Mar 2007 18:50:35 GMT From: Matt Jacob <mjacob@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 115354 for review Message-ID: <200703051850.l25IoZ1C015735@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=115354 Change 115354 by mjacob@mjexp on 2007/03/05 18:50:02 Do some integrate -i goop, including a hilarious 63 conflict change to hcall.S which I've never touched. Affected files ... .. //depot/projects/mjexp/sbin/geom/class/multipath/Makefile#3 integrate .. //depot/projects/mjexp/sbin/geom/class/multipath/geom_multipath.c#6 integrate .. //depot/projects/mjexp/sys/geom/multipath/g_multipath.c#15 integrate .. //depot/projects/mjexp/sys/geom/multipath/g_multipath.h#6 integrate .. //depot/projects/mjexp/sys/modules/geom/geom_multipath/Makefile#2 integrate .. //depot/projects/mjexp/sys/sun4v/sun4v/hcall.S#2 integrate Differences ... ==== //depot/projects/mjexp/sbin/geom/class/multipath/Makefile#3 (text+ko) ==== ==== //depot/projects/mjexp/sbin/geom/class/multipath/geom_multipath.c#6 (text+ko) ==== ==== //depot/projects/mjexp/sys/geom/multipath/g_multipath.c#15 (text+ko) ==== ==== //depot/projects/mjexp/sys/geom/multipath/g_multipath.h#6 (text+ko) ==== ==== //depot/projects/mjexp/sys/modules/geom/geom_multipath/Makefile#2 (text+ko) ==== ==== //depot/projects/mjexp/sys/sun4v/sun4v/hcall.S#2 (text+ko) ==== @@ -1,1437 +1,1852 @@ -/* - * CDDL HEADER START +/*- + * Copyright (c) 2006 Kip Macy <kmacy@FreeBSD.org> + * All rights reserved. * - * The contents of this file are subject to the terms of the - * Common Development and Distribution License, Version 1.0 only - * (the "License"). You may not use this file except in compliance - * with the License. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE - * or http://www.opensolaris.org/os/licensing. - * See the License for the specific language governing permissions - * and limitations under the License. + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. * - * When distributing Covered Code, include this CDDL HEADER in each - * file and include the License file at usr/src/OPENSOLARIS.LICENSE. - * If applicable, add the following below this CDDL HEADER, with the - * fields enclosed by brackets "[]" replaced with your own identifying - * information: Portions Copyright [yyyy] [name of copyright owner] - * - * CDDL HEADER END + * $FreeBSD: src/sys/sun4v/sun4v/hcall.S,v 1.18 2006/12/17 01:22:51 kmacy Exp $ */ -/* - * Copyright 2005 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. - */ -#pragma ident "@(#)hcall.s 1.10 05/09/28 SMI" - -/* - * Hypervisor calls - */ -#define _ASM - +#include <sys/cdefs.h> + #include <machine/asm.h> -__FBSDID("$FreeBSD: src/sys/sun4v/sun4v/hcall.S,v 1.1 2006/10/05 06:14:28 kmacy Exp $") - #include <machine/asi.h> #include <machine/asmacros.h> -#include <machine/hypervisor_api.h> +#include <machine/hypervisorvar.h> #include <machine/pstate.h> #include "assym.s" +/* + * Section 9 API Versioning + * + */ -#if defined(lint) -#error lint -#endif -#if defined(__lint) -#error __lint -#endif -#if defined(lint) || defined(__lint) +/* + * request and check for a version of the hypervisor apis + * which may be compatible + * + * arg0 api_group (%o0) + * arg1 major_number (%o1) + * arg2 req_minor_number (%o2) + * + * ret0 status (%o0) + * ret1 act_minor_number (%o1) + * + */ +ENTRY(api_set_version) + mov API_SET_VERSION, %o5 + ta CORE_TRAP + retl + stx %o1, [%o3] +END(api_set_version) -/*ARGSUSED*/ -int64_t -hv_cnputchar(uint8_t ch) -{ return (0); } +/* + * retrieve the major and minor number of the most recently + * successfully negotiated API + * + * arg0 api_group (%o0) + * + * ret0 status (%o0) + * ret1 major_number (%o1) + * ret2 major_number (%o2) + * + */ +ENTRY(api_get_version) + mov %o2, %o4 + mov %o1, %o3 + mov API_GET_VERSION, %o5 + ta CORE_TRAP + retl + stx %o1, [%o4] + +END(api_get_version) + +/* + * Section 10 Domain Services + * + */ -/*ARGSUSED*/ -int64_t -hv_cngetchar(uint8_t *ch) -{ return (0); } +/* + * stop all CPUs in the virtual machine domain and place them + * in the stopped state + * + * arg0 exit_code (%o0) + * + */ +ENTRY(hv_mach_exit) + mov MACH_EXIT, %o5 + ta FAST_TRAP + retl + nop +END(hv_mach_exit) + +/* + * copy the most current machine description into buffer + * upon success or EINVAL the service returns the actual + * size of the machine description + * + * arg0 buffer (%o0) + * arg1 length (%o1) + * + * ret0 status (%o0) + * ret1 length (%o1) + * + */ +ENTRY(hv_mach_desc) + mov %o1, %o2 + ldx [%o1], %o1 + mov MACH_DESC, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] +END(hv_mach_desc) -/*ARGSUSED*/ -uint64_t -hv_tod_get(uint64_t *seconds) -{ return (0); } +/* + * execute a software initiated reset of a virtual machine domain + * + */ +ENTRY(hv_mach_sir) + mov MACH_SIR, %o5 + ta FAST_TRAP + retl + nop +END(hv_mach_sir) + +/* + * report the guests soft state to the hypervisor + * + * arg0 soft_state (%o0) + * arg1 soft_state_desc_ptr (%o1) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mach_set_soft_state) + mov MACH_SET_SOFT_STATE, %o5 + ta FAST_TRAP + retl + nop +END(hv_mach_set_soft_state) + +/* + * retrieve the current value of the guest's software state + * + * arg0 soft_desc_ptr (%o0) + * + * ret0 status (%o0) + * arg1 soft_state (%o1) + * + */ +ENTRY(hv_mach_get_soft_state) + mov %o1, %o2 + mov MACH_SET_SOFT_STATE, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] +END(hv_mach_get_soft_state) + +/* + * set a watchdog timer, 0 disables, upon success + * time_remaining contains the time previously remaining + * + * arg0 timeout (%o0) + * + * ret0 status (%o0) + * ret1 time_remaining (%o1) + * + */ +ENTRY(hv_mach_watchdog) + mov %o1, %o2 + mov MACH_WATCHDOG, %o5 + ta FAST_TRAP + brnz,pn %o0, 1f + nop + stx %o1, [%o2] +1: retl + nop +END(hv_mach_watchdog) + +/* + * Section 11 CPU Services + * + */ -/*ARGSUSED*/ -uint64_t -hv_tod_set(uint64_t seconds) -{ return (0);} +/* + * start CPU with id cpuid with pc in %pc and real trap base address + * of rtba + * + * arg0 cpuid (%o0) + * arg1 pc (%o1) + * arg2 rtba (%o2) + * arg3 target_arg0 (%o3) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_cpu_start) + mov CPU_START, %o5 + ta FAST_TRAP + retl + nop +END(hv_cpu_start) -/*ARGSUSED*/ -uint64_t -hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) -{ return (0); } +/* + * stop CPU with id cpuid + * + * arg0 cpuid (%o0) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_cpu_stop) + mov CPU_STOP, %o5 + ta FAST_TRAP + retl + nop +END(hv_cpu_stop) -/*ARGSUSED*/ -uint64_t -hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) -{ return (0); } +/* + * set the real trap base address of the local cpu to rtba + * upon success the previous_rtba contains the address of the + * old rtba + * + * arg0 rtba (%o0) + * + * ret0 status (%o0) + * ret1 previous_rtba(%o1) + * + */ +ENTRY(hv_cpu_set_rtba) + mov %o1, %o2 + mov CPU_SET_RTBA, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] + +END(hv_cpu_set_rtba) -/*ARGSUSED*/ -uint64_t -hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) -{ return (0); } +/* + * return the current real trap base address + * + * ret0 status (%o0) + * ret1 rtba (%o1) + * + */ +ENTRY(hv_cpu_get_rtba) + mov CPU_GET_RTBA, %o5 + ta FAST_TRAP + retl + nop +END(hv_cpu_get_rtba) + +/* + * suspend execution on current cpu + * + * ret0 status (%o0) + * + */ +ENTRY(hv_cpu_yield) + mov CPU_YIELD, %o5 + ta FAST_TRAP + retl + nop +END(hv_cpu_yield) -/*ARGSUSED*/ -uint64_t -hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) -{ return (0); } +/* + * configure queue of size nentries to be placed at base raddr + * + * arg0 queue (%o0) + * arg1 base raddr (%o1) + * arg2 nentries (%o2) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_cpu_qconf) + mov CPU_QCONF, %o5 + ta FAST_TRAP + retl + nop +END(hv_cpu_qconf) + +/* + * return configuration of queue queue + * + * arg0 queue (%o0) + * + * ret0 status (%o0) + * ret1 base raddr (%o1) + * ret2 nentries (%o2) + * + */ +ENTRY(hv_cpu_qinfo) +END(hv_cpu_qinfo) + +/* + * send cpu mondo interrupt to cpulist + * + * arg0 ncpus (%o0) + * arg1 cpu list ra (%o1) + * arg2 mondo data ra(%o2) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_cpu_mondo_send) + ldx [PCPU(MONDO_DATA_RA)], %o2 + mov CPU_MONDO_SEND, %o5 + ta FAST_TRAP + retl + membar #Sync +END(hv_cpu_mondo_send) -#ifdef SET_MMU_STATS -/*ARGSUSED*/ -uint64_t -hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) -{ return (0); } -#endif /* SET_MMU_STATS */ +/* + * return the hypervisor id for the current cpu + * + * ret0 status (%o0) + * ret1 cpuid (%o1) + * + */ +ENTRY(hv_cpu_myid) + mov %o0, %o2 + mov CPU_MYID, %o5 + ta FAST_TRAP + stx %o1, [%o2] + retl + nop +END(hv_cpu_myid) -/*ARGSUSED*/ -uint64_t -hv_cpu_qconf(int queue, uint64_t paddr, int size) -{ return (0); } +/* + * retrieve the current state of cpu cpuid + * + * arg0 cpuid (%o0) + * + * ret0 status (%o0) + * ret1 state (%o1) + * + */ +ENTRY(hv_cpu_state) + mov %o1, %o2 + mov CPU_STATE, %o5 + ta FAST_TRAP + stx %o1, [%o2] + retl + nop +END(hv_cpu_state) + +/* + * Section 12 MMU Services + * + */ + +/* + * set the tsb(s) for the current cpu for context 0 + * + * arg0 ntsb (%o0) + * arg1 tsbdptr (%o1) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_tsb_ctx0) + mov MMU_TSB_CTX0, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_tsb_ctx0) -/*ARGSUSED*/ -uint64_t -hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, - pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p) -{ return (0); } +/* + * set the tsb(s) for the current cpu for non-zero contexts + * + * arg0 ntsb (%o0) + * arg1 tsbptr (%o1) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_tsb_ctxnon0) + mov MMU_TSB_CTXNON0, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_tsb_ctxnon0) -/*ARGSUSED*/ -uint64_t -hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, - pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data) -{ return (0); } +/* + * demap any page mapping of virtual address vaddr in context ctx + * + * arg0 reserved (%o0) + * arg1 reserved (%o1) + * arg2 vaddr (%o2) + * arg3 ctx (%o3) + * arg4 flags (%o4) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_demap_page) + mov MMU_DEMAP_PAGE, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_demap_page) -/*ARGSUSED*/ -uint64_t -hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) -{ return (0); } +/* + * demap all non-permanent virtual address mappings in context ctx + * + * arg0 reserved (%o0) + * arg1 reserved (%o1) + * arg2 ctx (%o2) + * arg3 flags (%o3) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_demap_ctx) + mov MMU_DEMAP_CTX, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_demap_ctx) -/*ARGSUSED*/ -uint64_t -hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) -{ return (0); } +/* + * demap all non-permanent virtual address mappings for the current + * virtual cpu + * + * arg0 reserved (%o0) + * arg1 reserved (%o1) + * arg2 flags (%o2) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_demap_all) + mov MMU_DEMAP_ALL, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_demap_all) -/*ARGSUSED*/ -uint64_t -hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) -{ return (0); } +/* + * create a non-permanent mapping for the calling virtual cpu + * + * arg0 vaddr (%o0) + * arg1 context (%o1) + * arg2 TTE (%o2) + * arg3 flags (%o3) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_map_addr) + mov MMU_MAP_ADDR, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_map_addr) -/*ARGSUSED*/ -uint64_t -hvio_intr_getstate(uint64_t sysino, int *intr_state) -{ return (0); } +/* + * create a permanent mapping for the calling virtual cpu + * + * arg0 vaddr (%o0) + * arg1 reserved (%o1) + * arg2 TTE (%o2) + * arg3 flags (%o3) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_map_perm_addr) + mov MMU_MAP_PERM_ADDR, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_map_perm_addr) -/*ARGSUSED*/ -uint64_t -hvio_intr_setstate(uint64_t sysino, int intr_state) -{ return (0); } +/* + * demap virtual address vaddr in context ctx on current virtual cpu + * + * arg0 vaddr (%o0) + * arg1 ctx (%o1) + * arg2 flags (%o2) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_unmap_addr) + mov MMU_UNMAP_ADDR, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_unmap_addr) -/*ARGSUSED*/ -uint64_t -hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) -{ return (0); } +/* + * demap any permanent mapping at virtual address vaddr on current virtual cpu + * + * arg0 vaddr (%o0) + * arg1 reserved (%o1) + * arg2 flags (%o2) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_unmap_perm_addr) + mov %o1, %o2 + clr %o1 + mov MMU_UNMAP_PERM_ADDR, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_unmap_perm_addr) -/*ARGSUSED*/ -uint64_t -hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) -{ return (0); } +/* + * configure the MMU fault status area for the current virtual cpu + * + * arg0 raddr (%o0) + * + * ret0 status (%o0) + * ret1 prev_raddr (%o1) + * + */ +ENTRY(hv_mmu_fault_area_conf) + mov %o1, %o2 + mov MMU_FAULT_AREA_CONF, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] +END(hv_mmu_fault_area_conf) -/*ARGSUSED*/ -uint64_t -hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, - pages_t pages, io_attributes_t io_attributes, - io_page_list_t *io_page_list_p, pages_t *pages_mapped) -{ return (0); } +/* + * enable or disable virtual address translation for the current virtual cpu + * + * arg0 enable_flag (%o0) + * arg1 return_target (%o1) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_mmu_enable) + mov MMU_ENABLE, %o5 + ta FAST_TRAP + retl + nop +END(hv_mmu_enable) -/*ARGSUSED*/ -uint64_t -hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, - pages_t pages, pages_t *pages_demapped) -{ return (0); } +/* + * return the TSB configuration as previously defined by mmu_tsb_ctx0 + * + * arg0 maxtsbs (%o0) + * arg1 buffer_ra (%o1) + * + * ret0 status (%o0) + * ret1 ntsbs (%o1) + * + */ +ENTRY(hv_mmu_tsb_ctx0_info) + mov %o1, %o2 + mov MMU_TSB_CTX0_INFO, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] +END(hv_mmu_tsb_ctx0_info) -/*ARGSUSED*/ -uint64_t -hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, - io_attributes_t *attributes_p, r_addr_t *r_addr_p) -{ return (0); } +/* + * return the TSB configuration as previously defined by mmu_tsb_ctxnon0 + * + * arg0 maxtsbs (%o0) + * arg1 buffer_ra (%o1) + * + * ret0 status (%o0) + * ret1 ntsbs (%o1) + * + */ +ENTRY(hv_mmu_tsb_ctxnon0_info) + mov %o1, %o2 + mov MMU_TSB_CTXNON0_INFO, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] +END(hv_mmu_tsb_ctxnon0_info) -/*ARGSUSED*/ -uint64_t -hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, - io_attributes_t io_attributes, io_addr_t *io_addr_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, - uint64_t *data_p) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, - r_addr_t ra2, uint32_t *rdbk_status) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, - int io_sync_direction, size_t *bytes_synched) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, - uint_t msiq_rec_cnt) -{ return (0); } - -/*ARGSUSED*/ -uint64_t -hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, - uint_t *msiq_rec_cnt_p) -{ return (0); } +/* + * return the MMU fault status area defined for the current virtual cpu + * + * ret0 status (%o0) + * ret1 mmfsara (%o1) + * + */ +ENTRY(hv_mmu_fault_area_info) + mov %o0, %o2 + mov MMU_FAULT_AREA_INFO, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] -/*ARGSUSED*/ -uint64_t -hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_valid_state_t *msiq_valid_state) -{ return (0); } +END(hv_mmu_fault_area_info) -/*ARGSUSED*/ -uint64_t -hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_valid_state_t msiq_valid_state) -{ return (0); } +/* + * Section 13 Cache and Memory Services + * + */ -/*ARGSUSED*/ -uint64_t -hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_state_t *msiq_state) -{ return (0); } +/* + * zero from raddr to raddr+length-1 + * + * arg0 raddr (%o0) + * arg1 length (%o1) + * + * ret0 status (%o0) + * ret1 length scrubbed (%o1) + * + */ +ENTRY(hv_mem_scrub) + mov MEM_SCRUB, %o5 + ta FAST_TRAP + stx %o1, [%o2] + retl + nop +END(hv_mem_scrub) -/*ARGSUSED*/ -uint64_t -hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, - pci_msiq_state_t msiq_state) -{ return (0); } +/* + * for the memory address range from raddr to raddr+length-1 + * for the next access within that range from main system memory + * + * arg0 raddr (%o0) + * arg1 length (%o1) + * + * ret0 status (%o0) + * ret1 length synced (%o1) + * + */ +ENTRY(hv_mem_sync) + mov MEM_SYNC, %o5 + ta FAST_TRAP + stx %o1, [%o2] + retl + nop +END(hv_mem_sync) -/*ARGSUSED*/ -uint64_t -hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, - msiqhead_t *msiq_head) -{ return (0); } +/* + * Section 14 Device Interrupt Services + * + */ -/*ARGSUSED*/ -uint64_t -hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, - msiqhead_t msiq_head) -{ return (0); } +/* + * converts a device specific interrupt number given by + * devhandle and devino to a system specific ino (sysino) + * + * arg0 devhandle (%o0) + * arg1 devino (%o1) + * + * ret0 status (%o0) + * ret1 sysino (%o1) + * + */ +ENTRY(hv_intr_devino_to_sysino) + mov INTR_DEVINO2SYSINO, %o5 + ta FAST_TRAP + retl + stx %o1, [%o2] +END(hv_intr_devino_to_sysino) -/*ARGSUSED*/ -uint64_t -hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, - msiqtail_t *msiq_tail) -{ return (0); } +/* + * return intr enabled state + * + * arg0 sysino (%o0) + * + * ret0 status (%o0) + * ret1 intr_enabled (%o1) + * + */ +ENTRY(hv_intr_getenabled) + mov %o1, %o2 + mov INTR_GETENABLED, %o5 + ta FAST_TRAP + retl + st %o1, [%o2] +END(hv_intr_getenabled) -/*ARGSUSED*/ -uint64_t -hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, - msiqid_t *msiq_id) -{ return (0); } +/* + * set intr enabled state + * + * arg0 sysino (%o0) + * arg1 intr_enabled (%o1) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_intr_setenabled) + mov INTR_SETENABLED, %o5 + ta FAST_TRAP + retl + nop +END(hv_intr_setenabled) -/*ARGSUSED*/ -uint64_t -hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, - msiqid_t msiq_id, msi_type_t msitype) -{ return (0); } +/* + * return current state of the interrupt given + * by the sysino + * + * arg0 sysino (%o0) + * + * ret0 status (%o0) + * ret1 intr_state (%o1) + * + */ +ENTRY(hv_intr_getstate) + mov %o1, %o2 + mov INTR_GETSTATE, %o5 + ta FAST_TRAP + retl + st %o1, [%o2] +END(hv_intr_getstate) -/*ARGSUSED*/ -uint64_t -hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, - pci_msi_valid_state_t *msi_valid_state) -{ return (0); } +/* + * set the current state of the interrupt given + * by the sysino + * + * arg0 sysino (%o0) + * arg1 intr_state (%o1) + * + * ret0 status (%o0) + * + */ +ENTRY(hv_intr_setstate) + mov INTR_SETSTATE, %o5 + ta FAST_TRAP + retl + nop +END(hv_intr_setstate) -/*ARGSUSED*/ -uint64_t -hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, - pci_msi_valid_state_t msi_valid_state) -{ return (0); } +/* + * return the cpuid that is the current target of the + * interrupt given by the sysino + * + * arg0 sysino (%o0) >>> TRUNCATED FOR MAIL (1000 lines) <<<
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