Date: Sat, 14 Sep 1996 16:43:54 -0700 From: "Michael L. VanLoon -- HeadCandy.com" <michaelv@MindBender.serv.net> To: Chuck Robey <chuckr@Glue.umd.edu> Cc: FreeBSD-smp@freebsd.org Subject: Re: Caching Message-ID: <199609142343.QAA08975@MindBender.serv.net> In-Reply-To: Your message of Sat, 14 Sep 96 18:48:54 -0400. <Pine.OSF.3.95.960914184354.5468B-100000@protocol.eng.umd.edu>
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>Can someone explain the added intricacies of caching in a multiprocessor
>environment a moment?
I'm not sure why you bring up multiprocessor, since none of your
questions specifically address that.
>I know this can be a really complicated subject if
>all the details are extruciatingly covered (write-thru, write-back, etc),
>but my question is really pointed at making me understand why it costs so
>much for a Pentium p6-200 if you include 512K of cache (it ups the price
>over 600 bucks per chip).
Actually, I don't think you're paying for the extra 256K of cache.
You're paying for supply and demand. Intel makes very few 512K chips;
they cost more.
>Does the old P5 incur the same penalty? Does
>not getting the p6 with cache make me incur a large penalty? Would a p5
>with cache be equivalently quicker, mhz for mhz, than a p6 without it?
Lots of questions, some which can't be answered with any real
authority.
I'm not sure what you mean by the P5 incuring the same penalty, when
the P5 can never be in the same circumstance (since it has no L2 cache
on the chip).
The P6 still has room to grow, where the P5 has topped out,
specifically because of the L2 cache being on the chip. The P5 L2
cache, being on the motherboard side of the bus, can run a maximum of
66MHz. It also must block if a cache miss occurs (so it can fetch the
memory and satisfy the read request).
The P6 cache, being in the chip package, runs at the full speed of the
processor (200MHz, for example). Plus, the P6 cache is non-blocking --
it can miss up to four requests before it blocks. Since the P6 is
capable of doing speculative and out-of-order execution, it can
continue to process instructions that are in the cache, if a previous
instruction caused a cache miss.
Read the Intel web site if you want more background on all this.
Would a P5 that had on-chip L2 cache be faster than a P6 of the same
speed without on-chip cache? Hard to call. But I don't think it's a
very realistic question since the chances are almost zero that Intel
will make a P5 with on-chip L2 cache. Their future is all P6, and the
P5 is now only a secondary market for them.
>Thats the kind of stuff I'm flailing around with, in trying to determine
>what kind of smp platform to buy. Help!
A P6 SMP platform is almost guaranteed to be faster than a P5 SMP
platform. And, even if it isn't significantly faster now, you will be
able to buy 300MHz, and maybe even 400MHz P6 chips to upgrade,
somewhere down the road.
The Pentium has topped out. 200MHz is pretty much the end of the line
for it. Sure, maybe AMD or Cyrix will eventually bring out a 300MHz
Pentium-like chip. But, its performance improvements, like the 133MHz
486 (5x86), will be dubious and slight.
-----------------------------------------------------------------------------
Michael L. VanLoon michaelv@MindBender.serv.net
--< Free your mind and your machine -- NetBSD free un*x >--
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NetBSD ports in progress: PICA, others...
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