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Date:      Sun, 22 Aug 1999 19:13:12 -0700 (PDT)
From:      Kevin Lynn <klynn@santacruz.org>
To:        freebsd-smp@freebsd.org
Subject:   Another SMP capable MB
Message-ID:  <Pine.BSF.4.10.9908221911480.480-100000@noc.santacruz.org>

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I've got SMP running on this N440BX hardware with 2 p2-400's and it's
absolutely rock solid.

Here's the mptable..


===============================================================================

MPTable, version 2.0.15

-------------------------------------------------------------------------------

MP Floating Pointer Structure:

  location:			BIOS
  physical address:		0x000f7300
  signature:			'_MP_'
  length:			16 bytes
  version:			1.4
  checksum:			0x4a
  mode:				Virtual Wire

-------------------------------------------------------------------------------

MP Config Table Header:

  physical address:		0x0009ed60
  signature:			'PCMP'
  base table length:		252
  version:			1.4
  checksum:			0x5d
  OEM ID:			'INTEL   '
  Product ID:			'N440BX      '
  OEM table pointer:		0x00000000
  OEM table size:		0
  entry count:			23
  local APIC address:		0xfee00000
  extended table length:	164
  extended table checksum:	206

-------------------------------------------------------------------------------

MP Config Base Table Entries:

--
Processors:	APIC ID	Version	State		Family	Model	Step	Flags
		 1	 0x11	 BSP, usable	 6	 5	 1	 0x183fbff
		 0	 0x11	 AP, usable	 6	 5	 1	 0x183fbff
--
Bus:		Bus ID	Type
		 0	 PCI   
		 1	 ISA   
--
I/O APICs:	APIC ID	Version	State		Address
		 2	 0x11	 usable		 0xfec00000
--
I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
		ExtINT	active-hi        edge	     1	   0	      2	   0
		INT	active-hi        edge	     1	   1	      2	   1
		INT	active-hi        edge	     1	   0	      2	   2
		INT	active-hi        edge	     1	   3	      2	   3
		INT	active-hi        edge	     1	   4	      2	   4
		INT	active-hi        edge	     1	   5	      2	   5
		INT	active-hi        edge	     1	   6	      2	   6
		INT	active-hi        edge	     1	   7	      2	   7
		INT	active-hi        edge	     1	   8	      2	   8
		INT	active-hi       level	     1	   9	      2	   9
		INT	active-hi       level	     1	  10	      2	  10
		INT	active-hi       level	     1	  11	      2	  11
		INT	active-hi        edge	     1	  12	      2	  12
		INT	active-hi        edge	     1	  13	      2	  13
		INT	active-hi        edge	     1	  14	      2	  14
		INT	active-hi        edge	     1	  15	      2	  15
--
Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
		ExtINT	active-hi        edge	     1	   0	    255	   0
		NMI	active-hi        edge	     0	 0:A	    255	   1

-------------------------------------------------------------------------------

MP Config Extended Table Entries:

--

 bus ID: 0 address type: I/O address
 address base: 0x0
 address range: 0x10000
--

 bus ID: 0 address type: memory address
 address base: 0x10000000
 address range: 0xea100000
--

 bus ID: 0 address type: prefetch address
 address base: 0xfa100000
 address range: 0x3f00000
--

 bus ID: 0 address type: memory address
 address base: 0xfe000000
 address range: 0xe00000
--

 bus ID: 0 address type: memory address
 address base: 0xfef00000
 address range: 0x1100000
--

 bus ID: 0 address type: memory address
 address base: 0xa0000
 address range: 0x20000
--

 bus ID: 0 address type: memory address
 address base: 0xd0000
 address range: 0x18000
--

 bus ID: 1 bus info: 0x01 parent bus ID: 0--

 bus ID: 0 address modifier: add
 predefined range: 0x00000000--

 bus ID: 0 address modifier: add
 predefined range: 0x00000001
-------------------------------------------------------------------------------

# SMP kernel config file options:


# Required:
options		SMP			# Symmetric MultiProcessor Kernel
options		APIC_IO			# Symmetric (APIC) I/O

# Optional (built-in defaults will work in most cases):
#options		NCPU=2			# number of CPUs
#options		NBUS=2			# number of busses
#options		NAPIC=1			# number of IO APICs
#options		NINTR=24		# number of INTs

===============================================================================




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