Date: Sat, 12 Oct 2002 12:32:21 -0700 (PDT) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 19154 for review Message-ID: <200210121932.g9CJWLJT029016@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=19154 Change 19154 by jmallett@jmallett_thefather on 2002/10/12 12:31:51 Add vendor bits for MIPS support, including irix-core.c, which is not currently used, but may be in the future, for obvious reasons, and pe-mips, which probably won't be used in the future, but better safe than sorry. Hook up vendor bits properly to FreeBSD-gnu system, so that up to gas is known to build. Affected files ... .. //depot/projects/mips/contrib/binutils/bfd/coff-mips.c#2 edit .. //depot/projects/mips/contrib/binutils/bfd/cpu-mips.c#2 edit .. //depot/projects/mips/contrib/binutils/bfd/irix-core.c#1 add .. //depot/projects/mips/contrib/binutils/bfd/pe-mips.c#2 edit .. //depot/projects/mips/contrib/binutils/gas/config/e-mipsecoff.c#1 add .. //depot/projects/mips/contrib/binutils/gas/config/e-mipself.c#1 add .. //depot/projects/mips/contrib/binutils/gas/config/itbl-mips.h#1 add .. //depot/projects/mips/contrib/binutils/gas/config/tc-mips.c#1 add .. //depot/projects/mips/contrib/binutils/gas/config/tc-mips.h#1 add .. //depot/projects/mips/contrib/binutils/gas/config/te-tmips.h#1 add .. //depot/projects/mips/contrib/binutils/include/opcode/mips.h#2 edit .. //depot/projects/mips/contrib/binutils/opcodes/mips-dis.c#1 add .. //depot/projects/mips/contrib/binutils/opcodes/mips-opc.c#1 add .. //depot/projects/mips/contrib/binutils/opcodes/mips16-opc.c#1 add .. //depot/projects/mips/gnu/usr.bin/binutils/as/Makefile.inc0#3 edit .. //depot/projects/mips/gnu/usr.bin/binutils/as/mips-freebsd/itbl-cpu.h#2 edit .. //depot/projects/mips/gnu/usr.bin/binutils/libbfd/Makefile.mips#3 edit Differences ... ==== //depot/projects/mips/contrib/binutils/bfd/coff-mips.c#2 (text+ko) ==== @@ -1,6 +1,6 @@ /* BFD back-end for MIPS Extended-Coff files. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001 + 2000, 2001, 2002 Free Software Foundation, Inc. Original version by Per Bothner. Full support added by Ian Lance Taylor, ian@cygnus.com. @@ -819,8 +819,7 @@ output_bfd = symbol->section->output_section->owner; } - if (bfd_is_und_section (symbol->section) - && relocateable == false) + if (bfd_is_und_section (symbol->section) && ! relocateable) return bfd_reloc_undefined; /* We have to figure out the gp value, so that we can adjust the @@ -830,10 +829,10 @@ external symbol if we are producing relocateable output. */ gp = _bfd_get_gp_value (output_bfd); if (gp == 0 - && (relocateable == false + && (! relocateable || (symbol->flags & BSF_SECTION_SYM) != 0)) { - if (relocateable != false) + if (relocateable) { /* Make up a value. */ gp = symbol->section->output_section->vma + 0x4000; @@ -899,14 +898,14 @@ /* Adjust val for the final section location and GP value. If we are producing relocateable output, we don't want to do this for an external symbol. */ - if (relocateable == false + if (! relocateable || (symbol->flags & BSF_SECTION_SYM) != 0) val += relocation - gp; insn = (insn &~ (unsigned) 0xffff) | (val & 0xffff); bfd_put_32 (abfd, (bfd_vma) insn, (bfd_byte *) data + reloc_entry->address); - if (relocateable != false) + if (relocateable) reloc_entry->address += input_section->output_offset; /* Make sure it fit in 16 bits. */ @@ -2116,10 +2115,9 @@ bfd_size_type size; size = (bfd_size_type) sec->reloc_count * sizeof (long); - offsets = (long *) bfd_alloc (abfd, size); + offsets = (long *) bfd_zalloc (abfd, size); if (offsets == (long *) NULL) goto error_return; - memset (offsets, 0, (size_t) size); section_tdata->offsets = offsets; } @@ -2602,6 +2600,8 @@ /* Merging of sections is not done. */ #define _bfd_ecoff_bfd_merge_sections bfd_generic_merge_sections +#define _bfd_ecoff_bfd_discard_group bfd_generic_discard_group + extern const bfd_target ecoff_big_vec; const bfd_target ecoff_little_vec = ==== //depot/projects/mips/contrib/binutils/bfd/cpu-mips.c#2 (text+ko) ==== @@ -37,11 +37,8 @@ if (a->arch != b->arch) return NULL; - if (a->mach > b->mach) - return a; - - if (b->mach > a->mach) - return b; + /* Machine compatibility is checked in + _bfd_mips_elf_merge_private_bfd_data. */ return a; } ==== //depot/projects/mips/contrib/binutils/bfd/pe-mips.c#2 (text+ko) ==== ==== //depot/projects/mips/contrib/binutils/include/opcode/mips.h#2 (text+ko) ==== @@ -133,6 +133,16 @@ #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ #define OP_SH_CODE19 6 /* 19 bit wait code. */ #define OP_MASK_CODE19 0x7ffff +#define OP_SH_ALN 21 +#define OP_MASK_ALN 0x7 +#define OP_SH_VSEL 21 +#define OP_MASK_VSEL 0x1f + +/* Values in the 'VSEL' field. */ +#define MDMX_FMTSEL_IMM_QH 0x1d +#define MDMX_FMTSEL_IMM_OB 0x1e +#define MDMX_FMTSEL_VEC_QH 0x15 +#define MDMX_FMTSEL_VEC_OB 0x16 /* This structure holds information for a particular instruction. */ @@ -220,13 +230,21 @@ "f" 32 bit floating point constant "l" 32 bit floating point constant in .lit4 + MDMX instruction operands (note that while these use the FP register + fields, they accept both $fN and $vN names for the registers): + "O" MDMX alignment offset (OP_*_ALN) + "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" MDMX destination register (OP_*_FD) + "Y" MDMX source register (OP_*_FS) + "Z" MDMX source register (OP_*_FT) + Other: "()" parens surrounding optional value "," separates operands Characters used so far, for quick reference when adding more: "<>()," - "ABCDEFGHIJLMNPRSTUVW" + "ABCDEFGHIJLMNOPQRSTUVWXYZ" "abcdfhijklopqrstuvwxz" */ @@ -297,6 +315,10 @@ #define INSN_MULT 0x40000000 /* Instruction synchronize shared memory. */ #define INSN_SYNC 0x80000000 +/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ +#define INSN_READ_MDMX_ACC 0 +/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ +#define INSN_WRITE_MDMX_ACC 0 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ @@ -316,6 +338,16 @@ #define INSN_ISA32 0x00000200 #define INSN_ISA64 0x00000400 +/* Masks used for MIPS-defined ASEs. */ +#define INSN_ASE_MASK 0x0000f000 + +/* MIPS 16 ASE */ +#define INSN_MIPS16 0x00002000 +/* MIPS-3D ASE */ +#define INSN_MIPS3D 0x00004000 +/* MDMX ASE */ +#define INSN_MDMX 0x00008000 + /* Chip specific instructions. These are bitmasks. */ /* MIPS R4650 instruction. */ @@ -367,10 +399,10 @@ #define CPU_MIPS64 64 #define CPU_SB1 12310201 /* octal 'SB', 01. */ -/* Test for membership in an ISA including chip specific ISAs. - INSN is pointer to an element of the opcode table; ISA is the - specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. */ +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. */ #define OPCODE_IS_MEMBER(insn, isa, cpu) \ (((insn)->membership & isa) != 0 \ @@ -521,9 +553,13 @@ M_REM_3I, M_REMU_3, M_REMU_3I, + M_DROL, M_ROL, + M_DROL_I, M_ROL_I, + M_DROR, M_ROR, + M_DROR_I, M_ROR_I, M_S_DA, M_S_DOB, ==== //depot/projects/mips/gnu/usr.bin/binutils/as/Makefile.inc0#3 (text+ko) ==== @@ -14,7 +14,10 @@ output-file.c read.c sb.c stabs.c \ subsegs.c symbols.c write.c depend.c ehopt.c # DEO: why not used? -#SRCS+= itbl-ops.c +# jmallett: _Is_ used for MIPS. +.if ${TARGET_ARCH} == "mips" +SRCS+= itbl-lex.l itbl-ops.c itbl-parse.y +.endif # if a 64-bit platform... .if (${TARGET_ARCH} == "alpha" || ${TARGET_ARCH} == "ia64" || ${TARGET_ARCH} == "sparc64") WARNS= 0 ==== //depot/projects/mips/gnu/usr.bin/binutils/as/mips-freebsd/itbl-cpu.h#2 (text+ko) ==== @@ -3,4 +3,4 @@ /* Values for processors will be from 0 to NUMBER_OF_PROCESSORS-1 */ #define NUMBER_OF_PROCESSORS 1 -#include "itbl-ppc.h" +#include "itbl-mips.h" ==== //depot/projects/mips/gnu/usr.bin/binutils/libbfd/Makefile.mips#3 (text+ko) ==== @@ -1,7 +1,11 @@ # $FreeBSD: src/gnu/usr.bin/binutils/libbfd/Makefile.sparc64,v 1.5 2001/10/14 00:58:59 obrien Exp $ +# XXXMIPS COFF? IRIX_CORE? SRCS+= aout32.c \ + coff-mips.c \ cpu-mips.c \ + ecoff.c \ + ecofflink.c \ elf32-mips.c \ elf32-target.h \ elf32.c \ @@ -9,8 +13,9 @@ elf64-target.h \ elf64.c \ elflink.c \ - irix-core.c -VECS+= bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec irix_core_vec + elfxx-mips.c \ + elfxx-target.h +VECS+= bfd_elf32_bigmips_vec bfd_elf32_littlemips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec # XXXMIPS Conditionalie on the MACHINE/MACHINE_ARCH targetry to decide # whether elf{32,64}_{big,little}mips vectors. @@ -20,8 +25,7 @@ CFLAGS+= -DHAVE_bfd_elf32_bigmips_vec \ -DHAVE_bfd_elf32_littlemips_vec \ -DHAVE_bfd_elf64_bigmips_vec \ - -DHAVE_bfd_elf64_littlemips_vec \ - -DHAVE_irix_core_vec + -DHAVE_bfd_elf64_littlemips_vec CLEANFILES+= elf32-target.h elf64-target.h elf32-target.h: elfxx-target.h To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe p4-projects" in the body of the message
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