Date: Sun, 15 Sep 2013 09:49:33 GMT From: zcore@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r257361 - soc2013/zcore/head/usr.sbin/bhyve Message-ID: <201309150949.r8F9nXuK019329@socsvn.freebsd.org>
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Author: zcore Date: Sun Sep 15 09:49:33 2013 New Revision: 257361 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=257361 Log: consolidate debug printf Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c ============================================================================== --- soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sun Sep 15 09:49:12 2013 (r257360) +++ soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sun Sep 15 09:49:33 2013 (r257361) @@ -74,10 +74,13 @@ /* * Debug printf */ +#ifdef AHCI_DEBUG static FILE *dbg; #define dprintf(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) -#define DPRINTF(params) dprintf params -#define WPRINTF(params) dprintf params +#else +#define dprintf(format, arg...) +#endif +#define wprintf printf struct ahci_ioreq { struct blockif_req io_req; @@ -188,7 +191,7 @@ sc->is |= (1 << i); } - DPRINTF(("%s %x\n", __func__, sc->is)); + dprintf("%s %x\n", __func__, sc->is); if (sc->is && (sc->ghc & AHCI_GHC_IE)) pci_generate_msi(sc->asc_pi, 0); } @@ -218,7 +221,7 @@ irq = 0; break; default: - WPRINTF(("unsupported fis type %d\n", ft)); + wprintf("unsupported fis type %d\n", ft); return; } memcpy(p->rfis + offset, fis, len); @@ -883,11 +886,12 @@ { int i; - dprintf("ACMD:\n"); + dprintf("ACMD:"); for (i = 0; i < 16; i++) dprintf("%02x ", acmd[i]); dprintf("\n"); } + switch (acmd[0]) { case ATAPI_TEST_UNIT_READY: cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; @@ -1004,7 +1008,7 @@ handle_packet_cmd(p, slot, cfis); break; default: - WPRINTF(("Unsupported cmd:%02x\n", cfis[2])); + wprintf("Unsupported cmd:%02x\n", cfis[2]); p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; p->is |= AHCI_P_IX_TFE; p->ci &= ~(1 << slot); @@ -1025,12 +1029,11 @@ sc = p->pr_sc; hdr = p->cmd_lst + slot * AHCI_CL_SIZE; cfl = (hdr->flags & 0x1f) * 4; - dprintf("cfis length:%d prdt entries: %d\n", cfl, hdr->prdtl); cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); prdt = (struct ahci_prdt_entry *)(cfis + 0x80); - /* dump cfis, will be removed latter */ + dprintf("\ncfis:"); for (i = 0; i < cfl; i++) { if (i % 10 == 0) dprintf("\n"); @@ -1038,22 +1041,19 @@ } dprintf("\n"); - /* dump prdt, will be removed latter */ for (i = 0; i < hdr->prdtl; i++) { - dprintf("%d@%08"PRIx64", %d\n", prdt->dbc & 0x3fffff, prdt->dba, (prdt->dbc >> 31) & 0x1); + dprintf("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); prdt++; } if (cfis[0] != FIS_TYPE_REGH2D) { - WPRINTF(("Not a H2D FIS:%02x\n", cfis[0])); + wprintf("Not a H2D FIS:%02x\n", cfis[0]); return; } if (cfis[1] & 0x80) { - dprintf("command cfis\n"); handle_cmd(p, slot, cfis); } else { - dprintf("control cfis\n"); if (cfis[15] & (1 << 2)) p->reset = 1; else if (p->reset) { @@ -1092,7 +1092,7 @@ struct ahci_cmd_hdr *hdr; int ncq = 0; - DPRINTF(("%s %d\n", __func__, err)); + dprintf("%s %d\n", __func__, err); aior = br->br_param; p = aior->io_pr; @@ -1151,7 +1151,7 @@ } pthread_mutex_unlock(&sc->mtx); - DPRINTF(("%s exit\n", __func__)); + dprintf("%s exit\n", __func__); } static void @@ -1164,7 +1164,7 @@ struct ahci_ioreq *aior; struct ahci_cmd_hdr *hdr; - DPRINTF(("%s %d\n", __func__, err)); + dprintf("%s %d\n", __func__, err); aior = br->br_param; p = aior->io_pr; @@ -1212,7 +1212,7 @@ } pthread_mutex_unlock(&sc->mtx); - DPRINTF(("%s exit\n", __func__)); + dprintf("%s exit\n", __func__); } @@ -1255,9 +1255,9 @@ } str = cpy = strdup(opts); +#ifdef AHCI_DEBUG dbg = fopen("/tmp/log", "w+"); - DPRINTF(("pci_ahci initializing\n")); - +#endif sc = malloc(sizeof(struct pci_ahci_softc)); memset(sc, 0, sizeof(struct pci_ahci_softc)); pi->pi_arg = sc; @@ -1346,8 +1346,8 @@ offset = (offset - AHCI_OFFSET) % AHCI_STEP; struct ahci_port *p = &sc->port[port]; - DPRINTF(("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", - port, offset, value)); + dprintf("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", + port, offset, value); switch (offset) { case AHCI_P_CLB: p->clb = value; @@ -1408,7 +1408,7 @@ case AHCI_P_TFD: case AHCI_P_SIG: case AHCI_P_SSTS: - WPRINTF(("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset)); + wprintf("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); break; case AHCI_P_SCTL: if (!(p->cmd & AHCI_P_CMD_ST)) { @@ -1437,15 +1437,15 @@ static void pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) { - DPRINTF(("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", - offset, value)); + dprintf("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", + offset, value); switch (offset) { case AHCI_CAP: case AHCI_PI: case AHCI_VS: case AHCI_CAP2: - WPRINTF(("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset)); + wprintf("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); break; case AHCI_GHC: if (value & AHCI_GHC_HR) @@ -1480,7 +1480,7 @@ else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) pci_ahci_port_write(sc, offset, value); else - DPRINTF(("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset)); + wprintf("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); pthread_mutex_unlock(&sc->mtx); } @@ -1511,8 +1511,8 @@ value = 0; break; } - DPRINTF(("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", - offset, value)); + dprintf("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", + offset, value); return (value); } @@ -1551,8 +1551,8 @@ value = 0; break; } - DPRINTF(("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", - port, offset, value)); + dprintf("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", + port, offset, value); return value; } @@ -1575,7 +1575,7 @@ value = pci_ahci_port_read(sc, offset); else { value = 0; - DPRINTF(("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset)); + wprintf("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); } pthread_mutex_unlock(&sc->mtx);
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