Date: Sat, 1 Dec 2018 15:41:25 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r341365 - in vendor/llvm/dist-release_70: include/llvm/MC include/llvm/Support include/llvm/Transforms/Utils lib/CodeGen lib/MC lib/Target/Mips lib/Target/Mips/MCTargetDesc lib/Target/P... Message-ID: <201812011541.wB1FfPK2012119@repo.freebsd.org>
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Author: dim Date: Sat Dec 1 15:41:24 2018 New Revision: 341365 URL: https://svnweb.freebsd.org/changeset/base/341365 Log: Vendor import of llvm release_70 branch r348011: https://llvm.org/svn/llvm-project/llvm/branches/release_70@348011 Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-b-range.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/shrink-wrap-buildpairf64-extractelementf64.mir vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_1.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_2.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_3.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/scalar_vector_test_4.ll vendor/llvm/dist-release_70/test/DebugInfo/Mips/eh_frame.ll vendor/llvm/dist-release_70/test/Transforms/LCSSA/rewrite-existing-dbg-values.ll Modified: vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll vendor/llvm/dist-release_70/test/CodeGen/Mips/tls.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/build-vector-tests.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/load-v4i8-improved.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/power9-moves-and-splats.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/pr38087.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/qpx-load-splat.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/swaps-le-6.ll vendor/llvm/dist-release_70/test/CodeGen/PowerPC/vsx_insert_extract_le.ll vendor/llvm/dist-release_70/test/CodeGen/X86/mingw-comdats.ll vendor/llvm/dist-release_70/tools/llvm-exegesis/lib/CMakeLists.txt Modified: vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/MC/MCAsmBackend.h Sat Dec 1 15:41:24 2018 (r341365) @@ -165,6 +165,11 @@ class MCAsmBackend { (public) return 0; } + /// Check whether a given symbol has been flagged with MICROMIPS flag. + virtual bool isMicroMips(const MCSymbol *Sym) const { + return false; + } + /// Handles all target related code padding when starting to write a new /// basic block to an object file. /// Modified: vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/Support/GenericDomTreeConstruction.h Sat Dec 1 15:41:24 2018 (r341365) @@ -1186,6 +1186,20 @@ struct SemiNCAInfo { << '\t' << U << "\n"); LLVM_DEBUG(dbgs() << "\n"); + // Recalculate the DominatorTree when the number of updates + // exceeds a threshold, which usually makes direct updating slower than + // recalculation. We select this threshold proportional to the + // size of the DominatorTree. The constant is selected + // by choosing the one with an acceptable performance on some real-world + // inputs. + + // Make unittests of the incremental algorithm work + if (DT.DomTreeNodes.size() <= 100) { + if (NumLegalized > DT.DomTreeNodes.size()) + CalculateFromScratch(DT, &BUI); + } else if (NumLegalized > DT.DomTreeNodes.size() / 40) + CalculateFromScratch(DT, &BUI); + // If the DominatorTree was recalculated at some point, stop the batch // updates. Full recalculations ignore batch updates and look at the actual // CFG. Modified: vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdater.h Sat Dec 1 15:41:24 2018 (r341365) @@ -76,6 +76,10 @@ class SSAUpdater { (public) /// block. bool HasValueForBlock(BasicBlock *BB) const; + /// Return the value for the specified block if the SSAUpdater has one, + /// otherwise return nullptr. + Value *FindValueForBlock(BasicBlock *BB) const; + /// Construct SSA form, materializing a value that is live at the end /// of the specified block. Value *GetValueAtEndOfBlock(BasicBlock *BB); Modified: vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h ============================================================================== --- vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/include/llvm/Transforms/Utils/SSAUpdaterImpl.h Sat Dec 1 15:41:24 2018 (r341365) @@ -357,10 +357,9 @@ class SSAUpdaterImpl { (public) BBInfo *Info = *I; if (Info->DefBB != Info) { - // Record the available value at join nodes to speed up subsequent - // uses of this SSAUpdater for the same value. - if (Info->NumPreds > 1) - (*AvailableVals)[Info->BB] = Info->DefBB->AvailableVal; + // Record the available value to speed up subsequent uses of this + // SSAUpdater for the same value. + (*AvailableVals)[Info->BB] = Info->DefBB->AvailableVal; continue; } Modified: vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -1156,10 +1156,11 @@ MCSection *TargetLoweringObjectFileCOFF::SelectSection MCSymbol *Sym = TM.getSymbol(ComdatGV); StringRef COMDATSymName = Sym->getName(); - // Append "$symbol" to the section name when targetting mingw. The ld.bfd + // Append "$symbol" to the section name *before* IR-level mangling is + // applied when targetting mingw. This is what GCC does, and the ld.bfd // COFF linker will not properly handle comdats otherwise. if (getTargetTriple().isWindowsGNUEnvironment()) - raw_svector_ostream(Name) << '$' << COMDATSymName; + raw_svector_ostream(Name) << '$' << ComdatGV->getName(); return getContext().getCOFFSection(Name, Characteristics, Kind, COMDATSymName, Selection, UniqueID); Modified: vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/MC/MCExpr.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -524,6 +524,11 @@ static void AttemptToFoldSymbolOffsetDifference( if (Asm->isThumbFunc(&SA)) Addend |= 1; + // If symbol is labeled as micromips, we set low-bit to ensure + // correct offset in .gcc_except_table + if (Asm->getBackend().isMicroMips(&SA)) + Addend |= 1; + // Clear the symbol expr pointers to indicate we have folded these // operands. A = B = nullptr; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -25,6 +25,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCTargetOptions.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" @@ -566,6 +567,14 @@ bool MipsAsmBackend::shouldForceRelocation(const MCAss case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: return true; } +} + +bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { + if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Sym)) { + if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) + return true; + } + return false; } MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Sat Dec 1 15:41:24 2018 (r341365) @@ -25,6 +25,7 @@ class MCAssembler; struct MCFixupKindInfo; class MCObjectWriter; class MCRegisterInfo; +class MCSymbolELF; class Target; class MipsAsmBackend : public MCAsmBackend { @@ -90,6 +91,7 @@ class MipsAsmBackend : public MCAsmBackend { (public) bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override; + bool isMicroMips(const MCSymbol *Sym) const override; }; // class MipsAsmBackend } // namespace Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -15,6 +15,7 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSymbolELF.h" @@ -51,6 +52,22 @@ void MipsELFStreamer::EmitInstruction(const MCInst &In } createPendingLabelRelocs(); +} + +void MipsELFStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { + Frame.Begin = getContext().createTempSymbol(); + MCELFStreamer::EmitLabel(Frame.Begin); +} + +MCSymbol *MipsELFStreamer::EmitCFILabel() { + MCSymbol *Label = getContext().createTempSymbol("cfi", true); + MCELFStreamer::EmitLabel(Label); + return Label; +} + +void MipsELFStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { + Frame.End = getContext().createTempSymbol(); + MCELFStreamer::EmitLabel(Frame.End); } void MipsELFStreamer::createPendingLabelRelocs() { Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h Sat Dec 1 15:41:24 2018 (r341365) @@ -26,6 +26,7 @@ class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCSubtargetInfo; +struct MCDwarfFrameInfo; class MipsELFStreamer : public MCELFStreamer { SmallVector<std::unique_ptr<MipsOptionRecord>, 8> MipsOptionRecords; @@ -59,6 +60,12 @@ class MipsELFStreamer : public MCELFStreamer { (public /// directives are emitted. void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; void EmitIntValue(uint64_t Value, unsigned Size) override; + + // Overriding these functions allows us to avoid recording of these labels + // in EmitLabel and later marking them as microMIPS. + void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *EmitCFILabel() override; /// Emits all the option records stored up until the point it's called. void EmitMipsOptionRecords(); Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MicroMips32r6InstrInfo.td Sat Dec 1 15:41:24 2018 (r341365) @@ -1733,7 +1733,7 @@ defm S_MMR6 : Cmp_Pats<f32, NOR_MMR6, ZERO>, ISA_MICRO defm D_MMR6 : Cmp_Pats<f64, NOR_MMR6, ZERO>, ISA_MICROMIPS32R6; def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6; -def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1 ZERO))>, ISA_MICROMIPS32R6; +def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6 (MTC1_MMR6 ZERO))>, ISA_MICROMIPS32R6; def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_W_D_MMR6 FGR64Opnd:$src)>, ISA_MICROMIPS32R6; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/Mips64InstrInfo.td Sat Dec 1 15:41:24 2018 (r341365) @@ -838,7 +838,7 @@ def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$ (SUBu GPR32:$src, GPR32:$src2), sub_32)>; def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), - (MUL GPR32:$src, GPR32:$src2), sub_32)>; + (MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS3_NOT_32R6_64R6; def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (PseudoMFHI ACC64:$src), sub_32)>; @@ -1139,3 +1139,6 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rs) "sltu\t$rs, $rt, $imm">, GPR_64; def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)>, GPR_64; + +def : MipsInstAlias<"rdhwr $rt, $rs", + (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/Mips64r6InstrInfo.td Sat Dec 1 15:41:24 2018 (r341365) @@ -301,6 +301,9 @@ def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i // Patterns used for matching away redundant sign extensions. // MIPS32 arithmetic instructions sign extend their result implicitly. +def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (MUL_R6 GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; def : MipsPat<(i64 (sext (i32 (sdiv GPR32:$src, GPR32:$src2)))), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (DIV GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS64R6; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsFastISel.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -953,6 +953,11 @@ bool MipsFastISel::selectBranch(const Instruction *I) MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; // For now, just try the simplest case where it's fed by a compare. if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { + MVT CIMVT = + TLI.getValueType(DL, CI->getOperand(0)->getType(), true).getSimpleVT(); + if (CIMVT == MVT::i1) + return false; + unsigned CondReg = getRegForValue(CI); BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) .addReg(CondReg) Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsInstrFPU.td Sat Dec 1 15:41:24 2018 (r341365) @@ -485,14 +485,14 @@ let AdditionalPredicates = [NotInMicroMips] in { def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, ISA_MIPS1; - def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, - bitconvert>, MFC1_FM<0>, ISA_MIPS1; + def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, + bitconvert>, MFC1_FM<0>, ISA_MIPS1; def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; } - def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, - bitconvert>, MFC1_FM<4>, ISA_MIPS1; + def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, + bitconvert>, MFC1_FM<4>, ISA_MIPS1; def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, ISA_MIPS1, FGR_64 { let DecoderNamespace = "MipsFP64"; Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEFrameLowering.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -299,8 +299,12 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBloc // register). Unfortunately, we have to make this decision before register // allocation so for now we use a spill/reload sequence for all // double-precision values in regardless of being an odd/even register. - if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || - (FP64 && !Subtarget.useOddSPReg())) { + // + // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as + // implicit operand, so other passes (like ShrinkWrapping) are aware that + // stack is used. + if (I->getNumOperands() == 4 && I->getOperand(3).isReg() + && I->getOperand(3).getReg() == Mips::SP) { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(); unsigned HiReg = I->getOperand(2).getReg(); @@ -360,9 +364,12 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasi // register). Unfortunately, we have to make this decision before register // allocation so for now we use a spill/reload sequence for all // double-precision values in regardless of being an odd/even register. - - if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || - (FP64 && !Subtarget.useOddSPReg())) { + // + // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as + // implicit operand, so other passes (like ShrinkWrapping) are aware that + // stack is used. + if (I->getNumOperands() == 4 && I->getOperand(3).isReg() + && I->getOperand(3).getReg() == Mips::SP) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = Op1.getReg(); unsigned N = Op2.getImm(); Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -238,6 +238,18 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(Mach case Mips::WRDSP: addDSPCtrlRegOperands(true, MI, MF); break; + case Mips::BuildPairF64_64: + case Mips::ExtractElementF64_64: + if (!Subtarget->useOddSPReg()) { + MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); + break; + } + // fallthrough + case Mips::BuildPairF64: + case Mips::ExtractElementF64: + if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1()) + MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true)); + break; default: replaceUsesWithZeroReg(MRI, MI); } Modified: vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/Mips/MipsSEInstrInfo.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -25,9 +25,14 @@ using namespace llvm; +static unsigned getUnconditionalBranch(const MipsSubtarget &STI) { + if (STI.inMicroMipsMode()) + return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; + return STI.isPositionIndependent() ? Mips::B : Mips::J; +} + MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) - : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), - RI() {} + : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {} const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { return RI; @@ -643,7 +648,7 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || - Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || + Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || Modified: vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/PowerPC/P9InstrResources.td Sat Dec 1 15:41:24 2018 (r341365) @@ -592,6 +592,7 @@ def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP XXPERM, XXPERMR, XXSLDWI, + XXSLDWIs, XXSPLTIB, XXSPLTW, XXSPLTWs, Modified: vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCISelLowering.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -8454,17 +8454,6 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) { int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG); - // If the source for the shuffle is a scalar_to_vector that came from a - // 32-bit load, it will have used LXVWSX so we don't need to splat again. - if (Subtarget.hasP9Vector() && - ((isLittleEndian && SplatIdx == 3) || - (!isLittleEndian && SplatIdx == 0))) { - SDValue Src = V1.getOperand(0); - if (Src.getOpcode() == ISD::SCALAR_TO_VECTOR && - Src.getOperand(0).getOpcode() == ISD::LOAD && - Src.getOperand(0).hasOneUse()) - return V1; - } SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv, DAG.getConstant(SplatIdx, dl, MVT::i32)); Modified: vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td ============================================================================== --- vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Target/PowerPC/PPCInstrVSX.td Sat Dec 1 15:41:24 2018 (r341365) @@ -877,6 +877,12 @@ let Uses = [RM] in { "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, imm32SExt16:$SHW))]>; + + let isCodeGenOnly = 1 in + def XXSLDWIs : XX3Form_2s<60, 2, + (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), + "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; + def XXSPLTW : XX2Form_2<60, 164, (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), "xxspltw $XT, $XB, $UIM", IIC_VecPerm, @@ -886,6 +892,7 @@ let Uses = [RM] in { def XXSPLTWs : XX2Form_2<60, 164, (outs vsrc:$XT), (ins vfrc:$XB, u2imm:$UIM), "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; + } // hasSideEffects } // UseVSXReg = 1 @@ -1466,8 +1473,6 @@ let AddedComplexity = 400 in { // Prefer VSX patterns (f64 (PPCmtvsra (i64 (vector_extract v2i64:$S, 1)))))), (f32 (XSCVUXDSP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>; } - def : Pat<(v4i32 (scalar_to_vector ScalarLoads.Li32)), - (v4i32 (XXSPLTWs (LIWAX xoaddr:$src), 1))>; // Instructions for converting float to i64 feeding a store. let Predicates = [NoP9Vector] in { @@ -3050,14 +3055,48 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] (STXVX $rS, xoaddr:$dst)>; def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst), (STXVX $rS, xoaddr:$dst)>; - def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), - (v4i32 (LXVWSX xoaddr:$src))>; - def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), - (v4f32 (LXVWSX xoaddr:$src))>; - def : Pat<(v4f32 (scalar_to_vector - (f32 (fpround (f64 (extloadf32 xoaddr:$src)))))), - (v4f32 (LXVWSX xoaddr:$src))>; + let AddedComplexity = 400 in { + // LIWAX - This instruction is used for sign extending i32 -> i64. + // LIWZX - This instruction will be emitted for i32, f32, and when + // zero-extending i32 to i64 (zext i32 -> i64). + let Predicates = [IsLittleEndian] in { + + def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), + (v4i32 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + + def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), + (v4f32 (XXPERMDIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 2))>; + } + + let Predicates = [IsBigEndian] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (sextloadi32 xoaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (LIWAX xoaddr:$src), VSRC))>; + + def : Pat<(v2i64 (scalar_to_vector (i64 (zextloadi32 xoaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC))>; + + def : Pat<(v4i32 (scalar_to_vector (i32 (load xoaddr:$src)))), + (v4i32 (XXSLDWIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; + + def : Pat<(v4f32 (scalar_to_vector (f32 (load xoaddr:$src)))), + (v4f32 (XXSLDWIs + (COPY_TO_REGCLASS (LIWZX xoaddr:$src), VSRC), 1))>; + } + + } + // Build vectors from i8 loads def : Pat<(v16i8 (scalar_to_vector ScalarLoads.Li8)), (v16i8 (VSPLTBs 7, (LXSIBZX xoaddr:$src)))>; @@ -3218,6 +3257,39 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), (f32 (DFLOADf32 ixaddr:$src))>; + + let AddedComplexity = 400 in { + // The following pseudoinstructions are used to ensure the utilization + // of all 64 VSX registers. + let Predicates = [IsLittleEndian, HasP9Vector] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddr:$src)))), + (v2i64 (XXPERMDIs + (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC), 2))>; + + def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + (v2f64 (XXPERMDIs + (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC), 2))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddr:$src)))), + (v2f64 (XXPERMDIs + (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC), 2))>; + } + + let Predicates = [IsBigEndian, HasP9Vector] in { + def : Pat<(v2i64 (scalar_to_vector (i64 (load ixaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2i64 (scalar_to_vector (i64 (load xaddr:$src)))), + (v2i64 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC))>; + + def : Pat<(v2f64 (scalar_to_vector (f64 (load ixaddr:$src)))), + (v2f64 (COPY_TO_REGCLASS (DFLOADf64 ixaddr:$src), VSRC))>; + def : Pat<(v2f64 (scalar_to_vector (f64 (load xaddr:$src)))), + (v2f64 (COPY_TO_REGCLASS (XFLOADf64 xaddr:$src), VSRC))>; + } + } + let Predicates = [IsBigEndian, HasP9Vector] in { // (Un)Signed DWord vector extract -> QP @@ -3932,3 +4004,4 @@ let AddedComplexity = 400 in { (v4i32 (VEXTSH2W $A))>; } } + Modified: vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Transforms/Utils/LCSSA.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -41,6 +41,7 @@ #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/PredIteratorCache.h" #include "llvm/Pass.h" #include "llvm/Transforms/Utils.h" @@ -199,6 +200,21 @@ bool llvm::formLCSSAForInstructions(SmallVectorImpl<In // Otherwise, do full PHI insertion. SSAUpdate.RewriteUse(*UseToRewrite); + } + + SmallVector<DbgValueInst *, 4> DbgValues; + llvm::findDbgValues(DbgValues, I); + + // Update pre-existing debug value uses that reside outside the loop. + auto &Ctx = I->getContext(); + for (auto DVI : DbgValues) { + BasicBlock *UserBB = DVI->getParent(); + if (InstBB == UserBB || L->contains(UserBB)) + continue; + // We currently only handle debug values residing in blocks where we have + // inserted a PHI instruction. + if (Value *V = SSAUpdate.FindValueForBlock(UserBB)) + DVI->setOperand(0, MetadataAsValue::get(Ctx, ValueAsMetadata::get(V))); } // SSAUpdater might have inserted phi-nodes inside other loops. We'll need Modified: vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp ============================================================================== --- vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/lib/Transforms/Utils/SSAUpdater.cpp Sat Dec 1 15:41:24 2018 (r341365) @@ -64,6 +64,11 @@ bool SSAUpdater::HasValueForBlock(BasicBlock *BB) cons return getAvailableVals(AV).count(BB); } +Value *SSAUpdater::FindValueForBlock(BasicBlock *BB) const { + AvailableValsTy::iterator AVI = getAvailableVals(AV).find(BB); + return (AVI != getAvailableVals(AV).end()) ? AVI->second : nullptr; +} + void SSAUpdater::AddAvailableValue(BasicBlock *BB, Value *V) { assert(ProtoType && "Need to initialize SSAUpdater"); assert(ProtoType == V->getType() && Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,189 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: < %s -verify-machineinstrs | FileCheck %s + +define void @testeq(i32, i32) { +; CHECK-LABEL: testeq: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: beq $[[REG0]], $[[REG1]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp eq i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testne(i32, i32) { +; CHECK-LABEL: testne: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: bne $[[REG0]], $[[REG1]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ne i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testugt(i32, i32) { +; CHECK-LABEL: testugt: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ugt i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testuge(i32, i32) { +; CHECK-LABEL: testuge: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp uge i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testult(i32, i32) { +; CHECK-LABEL: testult: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ult i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testule(i32, i32) { +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: sltu $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp ule i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testsgt(i32, i32) { +; CHECK-LABEL: testsgt: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp sgt i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testsge(i32, i32) { +; CHECK-LABEL: testsge: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp sge i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testslt(i32, i32) { +; CHECK-LABEL: testslt: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG0]], $[[REG1]] +; CHECK: bnez $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp slt i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +define void @testsle(i32, i32) { +; CHECK-LABEL: testsle: +; CHECK: andi $[[REG0:[0-9]+]], $4, 1 +; CHECK: negu $[[REG0]], $[[REG0]] +; CHECK: andi $[[REG1:[0-9]+]], $5, 1 +; CHECK: negu $[[REG1]], $[[REG1]] +; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]] +; CHECK: beqz $[[REG2]], + %3 = trunc i32 %0 to i1 + %4 = trunc i32 %1 to i1 + %5 = icmp sle i1 %3, %4 + br i1 %5, label %end, label %trap +trap: + call void @llvm.trap() + br label %end +end: + ret void +} + + +declare void @llvm.trap() Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,32 @@ +; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ +; RUN: -mcpu=mips32 -mattr=+fpxx \ +; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP + +; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ +; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \ +; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP + +; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \ +; RUN: -mcpu=mips32r2 -mattr=+fpxx \ +; RUN: -stop-after=expand-isel-pseudos | \ +; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP + +define double @foo2(i32 signext %v1, double %d1) { +entry: +; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp +; FPXX-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp +; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp +; FP64-IMPLICIT-SP: ExtractElementF64_64 killed %{{[0-9]+}}, 1, implicit $sp +; NO-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}} +; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp +; NO-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1 +; NO-IMPLICIT-SP-NOT: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp + %conv = fptrunc double %d1 to float + %0 = tail call float @llvm.copysign.f32(float 1.000000e+00, float %conv) + %conv1 = fpext float %0 to double + ret double %conv1 +} + +declare float @llvm.copysign.f32(float, float) Modified: vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll ============================================================================== --- vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll Sat Dec 1 14:20:32 2018 (r341364) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/longbranch.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -231,16 +231,13 @@ define void @test1(i32 signext %s) { ; MICROMIPSSTATIC: # %bb.0: # %entry ; MICROMIPSSTATIC-NEXT: bnezc $4, $BB0_2 ; MICROMIPSSTATIC-NEXT: # %bb.1: # %entry -; MICROMIPSSTATIC-NEXT: j $BB0_4 -; MICROMIPSSTATIC-NEXT: nop -; MICROMIPSSTATIC-NEXT: $BB0_2: # %entry ; MICROMIPSSTATIC-NEXT: j $BB0_3 ; MICROMIPSSTATIC-NEXT: nop -; MICROMIPSSTATIC-NEXT: $BB0_3: # %then +; MICROMIPSSTATIC-NEXT: $BB0_2: # %then ; MICROMIPSSTATIC-NEXT: lui $1, %hi(x) ; MICROMIPSSTATIC-NEXT: li16 $2, 1 ; MICROMIPSSTATIC-NEXT: sw $2, %lo(x)($1) -; MICROMIPSSTATIC-NEXT: $BB0_4: # %end +; MICROMIPSSTATIC-NEXT: $BB0_3: # %end ; MICROMIPSSTATIC-NEXT: jrc $ra ; ; MICROMIPSR6STATIC-LABEL: test1: Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-b-range.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-b-range.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,98 @@ +; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \ +; RUN: -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s + +; CHECK-LABEL: foo: +; CHECK-NEXT: 0: 41 a2 00 00 lui $2, 0 +; CHECK-NEXT: 4: 30 42 00 00 addiu $2, $2, 0 +; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25 +; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2) +; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2) +; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44 <foo+0x3e> +; CHECK-NEXT: 16: 00 00 00 00 nop +; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 1e: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 22: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 26: 40 60 00 02 bal 8 <foo+0x2e> +; CHECK-NEXT: 2a: 30 21 04 68 addiu $1, $1, 1128 +; CHECK-NEXT: 2e: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 32: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 36: 00 01 0f 3c jr $1 +; CHECK-NEXT: 3a: 33 bd 00 08 addiu $sp, $sp, 8 +; CHECK-NEXT: 3e: 94 00 00 02 b 8 <foo+0x46> +; CHECK-NEXT: 42: 00 00 00 00 nop +; CHECK-NEXT: 46: 30 20 4e 1f addiu $1, $zero, 19999 +; CHECK-NEXT: 4a: b4 22 00 14 bne $2, $1, 44 <foo+0x76> +; CHECK-NEXT: 4e: 00 00 00 00 nop +; CHECK-NEXT: 52: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 56: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 5a: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 5e: 40 60 00 02 bal 8 <foo+0x66> +; CHECK-NEXT: 62: 30 21 04 5c addiu $1, $1, 1116 +; CHECK-NEXT: 66: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 6a: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 6e: 00 01 0f 3c jr $1 +; CHECK-NEXT: 72: 33 bd 00 08 addiu $sp, $sp, 8 +; CHECK-NEXT: 76: 30 20 27 0f addiu $1, $zero, 9999 +; CHECK-NEXT: 7a: 94 22 00 14 beq $2, $1, 44 <foo+0xa6> +; CHECK-NEXT: 7e: 00 00 00 00 nop +; CHECK-NEXT: 82: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 86: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 8a: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 8e: 40 60 00 02 bal 8 <foo+0x96> +; CHECK-NEXT: 92: 30 21 04 2c addiu $1, $1, 1068 +; CHECK-NEXT: 96: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 9a: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 9e: 00 01 0f 3c jr $1 +; CHECK-NEXT: a2: 33 bd 00 08 addiu $sp, $sp, 8 + +; CHECK: 10466: 00 00 00 00 nop +; CHECK-NEXT: 1046a: 94 00 00 02 b 8 <foo+0x10472> +; CHECK-NEXT: 1046e: 00 00 00 00 nop +; CHECK-NEXT: 10472: 33 bd ff f8 addiu $sp, $sp, -8 +; CHECK-NEXT: 10476: fb fd 00 00 sw $ra, 0($sp) +; CHECK-NEXT: 1047a: 41 a1 00 01 lui $1, 1 +; CHECK-NEXT: 1047e: 40 60 00 02 bal 8 <foo+0x10486> +; CHECK-NEXT: 10482: 30 21 04 00 addiu $1, $1, 1024 +; CHECK-NEXT: 10486: 00 3f 09 50 addu $1, $ra, $1 +; CHECK-NEXT: 1048a: ff fd 00 00 lw $ra, 0($sp) +; CHECK-NEXT: 1048e: 00 01 0f 3c jr $1 +; CHECK-NEXT: 10492: 33 bd 00 08 addiu $sp, $sp, 8 +; CHECK-NEXT: 10496: 94 00 00 02 b 8 <foo+0x1049e> + +@x = external global i32, align 4 + +define void @foo() { + %1 = load i32, i32* @x, align 4 + %2 = icmp sgt i32 %1, 0 + br i1 %2, label %la, label %lf + +la: + switch i32 %1, label %le [ + i32 9999, label %lb + i32 19999, label %lc + ] + +lb: + tail call void asm sideeffect ".space 0", ""() + br label %le + +lc: + tail call void asm sideeffect ".space 0", ""() + br label %le + +le: + tail call void asm sideeffect ".space 66500", ""() + br label %lg + +lf: + tail call void asm sideeffect ".space 0", ""() + br label %lg + +lg: + tail call void asm sideeffect ".space 0", ""() + br label %li + +li: + tail call void asm sideeffect ".space 0", ""() + ret void +} Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-gcc-except-table.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,37 @@ +; RUN: llc -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -O3 -filetype=obj < %s | llvm-objdump -s -j .gcc_except_table - | FileCheck %s + +; CHECK: Contents of section .gcc_except_table: +; CHECK-NEXT: 0000 ff9b1501 0c011100 00110e1f 011f1800 +; CHECK-NEXT: 0010 00010000 00000000 + +@_ZTIi = external constant i8* + +define dso_local i32 @main() local_unnamed_addr norecurse personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind + %0 = bitcast i8* %exception.i to i32* + store i32 5, i32* %0, align 16 + invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn + to label %.noexc unwind label %return + +.noexc: + unreachable + +return: + %1 = landingpad { i8*, i32 } + catch i8* null + %2 = extractvalue { i8*, i32 } %1, 0 + %3 = tail call i8* @__cxa_begin_catch(i8* %2) nounwind + tail call void @__cxa_end_catch() + ret i32 0 +} + +declare i32 @__gxx_personality_v0(...) + +declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr + +declare void @__cxa_end_catch() local_unnamed_addr + +declare i8* @__cxa_allocate_exception(i32) local_unnamed_addr + +declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr Added: vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_70/test/CodeGen/Mips/micromips-mtc-mfc.ll Sat Dec 1 15:41:24 2018 (r341365) @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=mips -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -show-mc-encoding < %s | FileCheck --check-prefix=MM2 %s +; RUN: llc -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -show-mc-encoding < %s | FileCheck --check-prefix=MM6 %s + +define double @foo(double %a, double %b) { +; MM2-LABEL: foo: +; MM2: # %bb.0: # %entry +; MM2-NEXT: mov.d $f0, $f12 # encoding: [0x54,0x0c,0x20,0x7b] +; MM2-NEXT: mtc1 $zero, $f2 # encoding: [0x54,0x02,0x28,0x3b] +; MM2-NEXT: mthc1 $zero, $f2 # encoding: [0x54,0x02,0x38,0x3b] +; MM2-NEXT: c.ule.d $f12, $f2 # encoding: [0x54,0x4c,0x05,0xfc] +; MM2-NEXT: bc1t $BB0_2 # encoding: [0x43,0xa0,A,A] +; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_PC16_S1 +; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00] +; MM2-NEXT: # %bb.1: # %entry +; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A] +; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1 +; MM2-NEXT: nop # encoding: [0x00,0x00,0x00,0x00] +; MM2-NEXT: $BB0_2: # %return +; MM2-NEXT: jrc $ra # encoding: [0x45,0xbf] +; +; MM6-LABEL: foo: +; MM6: # %bb.0: # %entry +; MM6-NEXT: mov.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x06] +; MM6-NEXT: mtc1 $zero, $f1 # encoding: [0x54,0x01,0x28,0x3b] +; MM6-NEXT: mthc1 $zero, $f1 # encoding: [0x54,0x01,0x38,0x3b] +; MM6-NEXT: cmp.ule.d $f1, $f12, $f1 # encoding: [0x54,0x2c,0x09,0xd5] +; MM6-NEXT: mfc1 $2, $f1 # encoding: [0x54,0x41,0x20,0x3b] +; MM6-NEXT: andi16 $2, $2, 1 # encoding: [0x2d,0x21] +; MM6-NEXT: jrc $ra # encoding: [0x45,0xbf] +entry: + %cmp = fcmp ogt double %a, 0.000000e+00 + br i1 %cmp, label %if.end, label %if.else + +if.else: + br label %return + +if.end: + %mul = fmul double %a, 2.000000e+00 + br label %return + +return: + ret double %a +} *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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