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Date:      Mon, 24 Mar 2003 12:04:38 -0500
From:      Jake Burkholder <jake@locore.ca>
To:        Hidetoshi Shimokawa <simokawa@sat.t.u-tokyo.ac.jp>
Cc:        freebsd-sparc <freebsd-sparc@FreeBSD.ORG>
Subject:   Re: PCI-PCI bridge
Message-ID:  <20030324120438.Z76446@locore.ca>
In-Reply-To: <ybswuiopzkr.wl@ett.sat.t.u-tokyo.ac.jp>; from simokawa@sat.t.u-tokyo.ac.jp on Tue, Mar 25, 2003 at 12:13:40AM %2B0900
References:  <ybsel4xqrrw.wl@ett.sat.t.u-tokyo.ac.jp> <20030324075708.X76446@locore.ca> <ybswuiopzkr.wl@ett.sat.t.u-tokyo.ac.jp>

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Apparently, On Tue, Mar 25, 2003 at 12:13:40AM +0900,
	Hidetoshi Shimokawa said words to the effect of;

> At Mon, 24 Mar 2003 07:57:08 -0500,
> Jake Burkholder wrote:
> > 
> > Apparently, On Mon, Mar 24, 2003 at 02:04:35PM +0900,
> > 	Hidetoshi Shimokawa said words to the effect of;
> > 
> > > Hi,
> > > 
> > > I have a problem with PCI-PCI bridge on sparc64(sun ultra5) while
> > > tesing firewire driver.
> > > 
> > > I have a Adaptec card which has a firewire and a USB2 chips behind
> > > PCI-PCI bridge. With this card the DMA trasfer speed is poor and
> > > it sometimes causes timeout which leads to panic(*1).
> > > 
> > > I finally found that this is because the PCI-PCI bridge 
> > > is not configured correctly and setting the cache line size in the
> > > bridge by pciconf fixes the problem.
> > > (pciconf -w -b  pci1:1:0 0x0c 16)
> > > 
> > > Sun's APB PCI-PCI bridges seem to be configured correctly but the one on
> > > the card doesn't.
> > > Who should configure such bridges?
> > > Does upgrading firmware fix the problem?
> > 
> > I think this is the firmware's job but it doesn't always do it.  Updating
> > the firmware may or may not help.  We try to fix this up on startup by
> > walking the device tree and initializing all the cache line size registers,
> > but I notice that we don't do it for subordinate bridges, only for their
> > child devices.
> > 
> > You might try something like this (untested):
> 
> Thanks, I'll try it tomorrow.
> 
> BTW, the latency timer and secondary(?) latency timer of the bridge
> are zero too. Shall we configure those values too?
> I don't observe significant performance change by changing those
> values though.

Yes, probably.  Again, currently the pci code tries to set the latency
timer of child devices correctly, but not the bridge itself.

Jake

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