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Date:      Wed, 2 May 2012 14:37:09 -0700
From:      Adrian Chadd <adrian@freebsd.org>
To:        freebsd-mips@freebsd.org
Subject:   heads up - ar71xx changes
Message-ID:  <CAJ-VmonZbXe3yUaBn3-giaz7aiMYsk3D4u%2BghbZUZkLWw595mQ@mail.gmail.com>

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Hi,

there's been a few ar71xx changes in the last few days. I'd appreciate
it if it got decent testing.

* The miibus/mdiobus (optional) split from Stefan Bethke as
preparation for the switch API;
* The MII clock speed is now set when the MAC PLL is programmed (based
on the port speed) - this happens for the AR71xx and AR913x. The
AR724x doesn't need this;
* New hints are available to override the PLL settings from the hard
programmed defaults (again based on port speed and chip);
* Allowed both arge0 and arge1's MII busses to be accessible - gonzo's
initial commit had both MACs use the MII bus on arge0 - which is fine
for AR71xx and AR913x, but not fine for AR724x (two MII busses) and
later AR93xx/AR94xx SoCs.
* A new hint is available which allows for the MII type (MII, RMII,
GMII,RGMII) to be forcibly set at attach time.

I've only tested this on the AR71xx + AR8316 switch PHY board. I
haven't yet tested it on any AR71xx + normal PHY (eg the Ubiquiti
LS-SR71) just to ensure that it works, but I'll do that tonight. I'll
also try it on the Routerstation board, just to make sure that still
works.

I would appreciate it if others using the AR71xx, AR724x or AR913x
embedded boards could give this a whirl and make sure ethernet still
works.

TODO (in case someone else would like to finish off ar724x support):

* Add the AR7242 PLL programming for arge0;
* Go through the ar724x fifo and PLL code in Linux Openwrt (dev-eth.c)
and ensure that our code (ar724x_chip.c and if_arge.c) does the
"right" things;
* When a forced speed/duplex is set via ifconfig, the MAC stops
successfully handling frames. I'll do some tests to see if I or others
broke this feature (I don't recall using anything except autoneg until
I first tried this a couple days ago) but it initially seems as if the
arge PLL isn't being programmed when a static speed/duplex is defined.

Thanks,



Adrian



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