Date: Fri, 26 Apr 2019 03:47:59 -0400 From: Mark Johnston <markj@freebsd.org> To: Konstantin Belousov <kostikbel@gmail.com> Cc: Wojciech Macek <wma@semihalf.com>, Wojciech Macek <wma@freebsd.org>, src-committers <src-committers@freebsd.org>, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r346593 - head/sys/sys Message-ID: <20190426074759.GA2695@spy> In-Reply-To: <20190426073836.GP12936@kib.kiev.ua> References: <201904230636.x3N6aWQK057863@repo.freebsd.org> <20190425040817.GA3789@spy> <CANsEV8ca_y9EGxRQGoi%2BCMbCBn-8cfw_MJcRtujgP7vE0n_JKQ@mail.gmail.com> <20190425082222.GJ12936@kib.kiev.ua> <20190426060456.GA59853@spy> <20190426073836.GP12936@kib.kiev.ua>
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On Fri, Apr 26, 2019 at 10:38:36AM +0300, Konstantin Belousov wrote: > On Fri, Apr 26, 2019 at 02:04:56AM -0400, Mark Johnston wrote: > > On Thu, Apr 25, 2019 at 11:22:22AM +0300, Konstantin Belousov wrote: > > > On Thu, Apr 25, 2019 at 07:38:21AM +0200, Wojciech Macek wrote: > > > > Intel does not reorder reads against the condition "if" here. I know for > > > > sure that ARM does, but therestill might be some other architectures that > > > > also suffers such behavior - I just don't have any means to verify. > > > > I remember the discussion for rS302292 where we agreed that this kind of > > > > patches should be the least impacting in perfomrance as possible. Adding > > > > unconditional memory barrier causes significant performance drop on Intel, > > > > where in fact, the issue was never seen. > > > > > > > Atomic_thread_fence_acq() is nop on x86, or rather, it is compiler memory > > > barrier. If you need read/read fence on some architectures, I am sure > > > that you need compiler barrier on all. > > > > To add a bit, one reason to prefer atomic(9) to explicit fences is > > precisely because it issues fences only when required by a given > > CPU architecture. There is no "unconditional memory barrier" added by > > the diff even without the #ifdef. > Well, atomic_thread_fence_acq() is the explicit fence. And on x86 it > does add unconditional compiler memory barrier. I only mean that with atomic_thread_fence_acq() on x86, the CPU does not see any fences. Based on the original commit it seems that a compiler barrier is required on all platforms, at a minimum.
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