Date: Sun, 24 Apr 2011 17:25:50 +0000 (UTC) From: Marcel Moolenaar <marcel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r220995 - in projects/altix/sys/ia64: include sgisn Message-ID: <201104241725.p3OHPoIP040651@svn.freebsd.org>
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Author: marcel Date: Sun Apr 24 17:25:50 2011 New Revision: 220995 URL: http://svn.freebsd.org/changeset/base/220995 Log: Commit WIP: o Create a console device (sncon) as a child of shub. We query SAL for the NASID of the node to which all console output is routed and map that onto the shub instance. In short: the sncon child exists only for the shub instance that corresponds to the master L1 node. o Define the registers of the PCI bridge and SHub controller and create tags and handles for accessing them. More power to us... Added: projects/altix/sys/ia64/sgisn/sgisn_pcib.h (contents, props changed) projects/altix/sys/ia64/sgisn/sgisn_shub.h (contents, props changed) Modified: projects/altix/sys/ia64/include/sgisn.h projects/altix/sys/ia64/sgisn/sgisn_pcib.c (contents, props changed) projects/altix/sys/ia64/sgisn/sgisn_shub.c (contents, props changed) Modified: projects/altix/sys/ia64/include/sgisn.h ============================================================================== --- projects/altix/sys/ia64/include/sgisn.h Sun Apr 24 17:13:42 2011 (r220994) +++ projects/altix/sys/ia64/include/sgisn.h Sun Apr 24 17:25:50 2011 (r220995) @@ -29,19 +29,21 @@ #define _MACHINE_SGISN_H_ /* SAL functions */ +#define SAL_SGISN_MASTER_NASID 0x02000004 #define SAL_SGISN_KLCFG_ADDR 0x02000005 #define SAL_SGISN_SAPIC_INFO 0x0200001d #define SAL_SGISN_SN_INFO 0x0200001e #define SAL_SGISN_PUTC 0x02000021 #define SAL_SGISN_GETC 0x02000022 #define SAL_SGISN_POLL 0x02000026 +#define SAL_SGISN_CON_INTR 0x02000027 #define SAL_SGISN_TXBUF 0x02000028 #define SAL_SGISN_IOHUB_INFO 0x02000055 #define SAL_SGISN_IOBUS_INFO 0x02000056 #define SAL_SGISN_IODEV_INFO 0x02000057 #define SAL_SGISN_FEATURE_GET_PROM 0x02000065 #define SAL_SGISN_FEATURE_SET_OS 0x02000066 - +#define SAL_SGISN_SET_CPUID 0x02000068 #define SGISN_HUB_NITTES 8 #define SGISN_HUB_NWIDGETS 16 @@ -77,6 +79,7 @@ struct sgisn_geoid { } sg_u; }; +struct sgisn_fwdev; struct sgisn_fwhub; struct sgisn_widget { @@ -101,12 +104,34 @@ struct sgisn_fwbus { struct sgisn_widget *bus_wgt_info; }; +struct sgisn_fwflush_dev { + uint32_t fld_bus; + uint32_t fld_slot; + uint32_t fld_pin; + uint32_t _pad; + struct { + uint64_t start; + uint64_t end; + } fld_bar[6]; + uint64_t *fld_intr; + uint64_t fld_value; + uint64_t *fld_flush; + uint32_t fld_pci_bus; + uint32_t fld_pci_segment; + struct sgisn_fwbus *fld_parent; + uint64_t fld_xxx; +}; + +struct sgisn_fwflush_widget { + struct sgisn_fwflush_dev flw_dev[32]; +}; + struct sgisn_fwhub { struct sgisn_geoid hub_geoid; uint16_t hub_nasid; uint16_t hub_peer_nasid; uint32_t _pad; - void *hub_widgets; + struct sgisn_fwflush_widget *hub_flush; uint64_t hub_dma_itte[SGISN_HUB_NITTES]; struct sgisn_widget hub_widget[SGISN_HUB_NWIDGETS]; @@ -119,17 +144,18 @@ struct sgisn_fwhub { struct sgisn_fwirq { uint64_t _obsolete; - uint16_t irq_tgt_nasid; + uint16_t irq_nasid; uint16_t _pad1; - uint32_t irq_tgt_slice; + uint32_t irq_slice; uint32_t irq_cpuid; uint32_t irq_nr; uint32_t irq_pin; - uint64_t irq_tgt_xtaddr; - uint32_t irq_br_type; uint32_t _pad2; + uint64_t irq_xtaddr; + uint32_t irq_br_type; + uint32_t _pad3; void *irq_bridge; /* Originating */ - void *irq_io_info; + struct sgisn_fwdev *irq_dev; uint32_t irq_last; uint32_t irq_cookie; uint32_t irq_flags; @@ -140,7 +166,8 @@ struct sgisn_fwdev { uint64_t dev_bar[6]; uint64_t dev_romaddr; uint64_t dev_handle; - uint64_t dev_os_private[3]; + struct sgisn_fwbus *dev_parent; + uint64_t dev_os_private[2]; struct sgisn_fwirq *dev_irq; uint64_t dev_xxx[4]; }; Modified: projects/altix/sys/ia64/sgisn/sgisn_pcib.c ============================================================================== --- projects/altix/sys/ia64/sgisn/sgisn_pcib.c Sun Apr 24 17:13:42 2011 (r220994) +++ projects/altix/sys/ia64/sgisn/sgisn_pcib.c Sun Apr 24 17:25:50 2011 (r220995) @@ -50,12 +50,17 @@ __FBSDID("$FreeBSD$"); #include <machine/sal.h> #include <machine/sgisn.h> +#include <ia64/sgisn/sgisn_pcib.h> + static struct sgisn_fwdev sgisn_dev; static struct sgisn_fwirq sgisn_irq; struct sgisn_pcib_softc { device_t sc_dev; - void *sc_promaddr; + struct sgisn_fwbus *sc_fwbus; + bus_addr_t sc_ioaddr; + bus_space_tag_t sc_tag; + bus_space_handle_t sc_hndl; u_int sc_domain; u_int sc_busnr; }; @@ -185,22 +190,36 @@ sgisn_pcib_activate_resource(device_t de device_printf(dev, "interrupt mismatch: (actual=%u)\n", sgisn_irq.irq_nr); - printf("XXX: %s: %u, %u, %u, %u, %u, %#lx\n", __func__, - sgisn_irq.irq_tgt_nasid, sgisn_irq.irq_tgt_slice, - sgisn_irq.irq_cpuid, sgisn_irq.irq_nr, sgisn_irq.irq_pin, - sgisn_irq.irq_tgt_xtaddr); - printf("\t%u, %p, %p, %u, %#x, %#x, %u\n", sgisn_irq.irq_br_type, - sgisn_irq.irq_bridge, sgisn_irq.irq_io_info, sgisn_irq.irq_last, - sgisn_irq.irq_cookie, sgisn_irq.irq_flags, sgisn_irq.irq_refcnt); + printf("XXX: nasid=%u, slice=%u, cpuid=%u, irq=%u, pin=%u, " + "xtaddr=%#lx\n", sgisn_irq.irq_nasid, sgisn_irq.irq_slice, + sgisn_irq.irq_cpuid, sgisn_irq.irq_nr, sgisn_irq.irq_pin, + sgisn_irq.irq_xtaddr); + printf("XXX: brt=%u, br=%p, dev=%p, last=%u, cookie=%#x, " + "flags=%#x, refcnt=%u\n", sgisn_irq.irq_br_type, + sgisn_irq.irq_bridge, sgisn_irq.irq_dev, + sgisn_irq.irq_last, sgisn_irq.irq_cookie, + sgisn_irq.irq_flags, sgisn_irq.irq_refcnt); #if 0 + intrs = bus_space_read_8(sc->sc_tag, sc->sc_hndl, + PIC_REG_INT_ENABLE); + intrs |= 1 << sgisn_irq.irq_pin; + bus_space_write_8(sc->sc_tag, sc->sc_hndl, PIC_REG_INT_ENABLE, + intrs); + + bus_space_write_8(sc->sc_tag, sc->sc_hndl, + PIC_REG_INT_PIN(sgisn_irq.irq_pin), 1); + + sgisn_dev.dev_parent = sc->sc_fwbus; + sgisn_dev.dev_irq = &sgisn_irq; + sgisn_irq.irq_dev = &sgisn_dev; + r = ia64_sal_entry(SAL_SGISN_INTERRUPT, 1 /*alloc*/, - sgisn_irq.irq_tgt_nasid, - (sgisn_irq.irq_bridge >> 24) & 15 + sgisn_irq.irq_nasid, (sgisn_irq.irq_bridge >> 24) & 15, ia64_tpa((uintptr_t)&sgisn_irq), paddr, - sgisn_irq.irq_tgt_nasid, - sgisn_irq.irq_tgt_slice); + sgisn_irq.irq_nasid, + sgisn_irq.irq_slice); if (r.status != 0) return (ENXIO); #endif @@ -250,7 +269,8 @@ sgisn_pcib_attach(device_t dev) { struct sgisn_pcib_softc *sc; device_t parent; - uintptr_t bus, seg; + uintptr_t addr, bus, seg; + u_int i; sc = device_get_softc(dev); sc->sc_dev = dev; @@ -261,6 +281,27 @@ sgisn_pcib_attach(device_t dev) BUS_READ_IVAR(parent, dev, SHUB_IVAR_PCISEG, &seg); sc->sc_domain = seg; + (void)ia64_sal_entry(SAL_SGISN_IOBUS_INFO, seg, bus, + ia64_tpa((uintptr_t)&addr), 0, 0, 0, 0); + sc->sc_fwbus = (void *)IA64_PHYS_TO_RR7(addr); + sc->sc_ioaddr = IA64_RR_MASK(sc->sc_fwbus->bus_base); + sc->sc_tag = IA64_BUS_SPACE_MEM; + bus_space_map(sc->sc_tag, sc->sc_ioaddr, PIC_REG_SIZE, 0, + &sc->sc_hndl); + + device_printf(dev, "ASIC=%x, XID=%u\n", sc->sc_fwbus->bus_asic, + sc->sc_fwbus->bus_xid); + + device_printf(dev, "INTR status=%lx\n", + bus_space_read_8(sc->sc_tag, sc->sc_hndl, PIC_REG_INT_STATUS)); + device_printf(dev, "INTR enable=%lx\n", + bus_space_read_8(sc->sc_tag, sc->sc_hndl, PIC_REG_INT_ENABLE)); + device_printf(dev, "INTR addrs:"); + for (i = 0; i < 8; i++) + printf(" %lx", bus_space_read_8(sc->sc_tag, sc->sc_hndl, + PIC_REG_INT_ADDR(i))); + printf("\n"); + #if 0 sgisn_pcib_scan(sc, sc->sc_busnr, sgisn_pcib_maxslots(dev)); #endif Added: projects/altix/sys/ia64/sgisn/sgisn_pcib.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/altix/sys/ia64/sgisn/sgisn_pcib.h Sun Apr 24 17:25:50 2011 (r220995) @@ -0,0 +1,76 @@ +/*- + * Copyright (c) 2011 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _IA64_SGISN_PCIB_H_ +#define _IA64_SGISN_PCIB_H_ + +#define PIC_REG_SIZE (512 * 1024) + +#define PIC_REG_WGT_ID 0x00000 +#define PIC_REG_WGT_STAT 0x00008 +#define PIC_REG_WGT_ERR_H 0x00010 +#define PIC_REG_WGT_ERR 0x00018 +#define PIC_REG_WGT_CTRL 0x00020 +#define PIC_REG_WGT_REQ_TOUT 0x00028 +#define PIC_REG_WGT_INT_H 0x00030 +#define PIC_REG_WGT_INT 0x00038 +#define PIC_REG_WGT_ERRCMD 0x00040 +#define PIC_REG_WGT_LLP 0x00048 +#define PIC_REG_WGT_TFLUSH 0x00050 +#define PIC_REG_WGT_AUX_ERR 0x00058 +#define PIC_REG_WGT_RSP_H 0x00060 +#define PIC_REG_WGT_RSP 0x00068 +#define PIC_REG_WGT_TSTPIN_CTL 0x00070 +#define PIC_REG_WGT_ADDR_LKERR 0x00078 + +#define PIC_REG_DIR_MAP 0x00080 +#define PIC_REG_MAP_FAULT 0x00090 +#define PIC_REG_ARBITRATION 0x000a0 +#define PIC_REG_ATE_PARERR 0x000b0 +#define PIC_REG_BUS_TOUT 0x000c0 +#define PIC_REG_PCI_CFG 0x000c8 +#define PIC_REG_PCI_ERR_H 0x000d0 +#define PIC_REG_PCI_ERR 0x000d8 + +#define PIC_REG_INT_STATUS 0x00100 +#define PIC_REG_INT_ENABLE 0x00108 +#define PIC_REG_INT_RSTSTAT 0x00110 +#define PIC_REG_INT_MODE 0x00118 +#define PIC_REG_INT_DEVICE 0x00120 +#define PIC_REG_INT_HOSTERR 0x00128 +#define PIC_REG_INT_ADDR(x) (0x00130 + (x << 3)) +#define PIC_REG_INT_ERRVIEW 0x00170 +#define PIC_REG_INT_MULTI 0x00178 +#define PIC_REG_INT_FORCE(x) (0x00180 + (x << 3)) +#define PIC_REG_INT_PIN(x) (0x001c0 + (x << 3)) + +#define PIC_REG_DEVICE(x) (0x00200 + (x << 3)) +#define PIC_REG_WR_REQ(x) (0x00240 + (x << 3)) +#define PIC_REG_RRB_MAP(x) (0x00280 + (x << 3)) + +#endif /* _IA64_SGISN_PCIB_H_ */ Modified: projects/altix/sys/ia64/sgisn/sgisn_shub.c ============================================================================== --- projects/altix/sys/ia64/sgisn/sgisn_shub.c Sun Apr 24 17:13:42 2011 (r220994) +++ projects/altix/sys/ia64/sgisn/sgisn_shub.c Sun Apr 24 17:25:50 2011 (r220995) @@ -49,11 +49,16 @@ __FBSDID("$FreeBSD$"); #include <contrib/dev/acpica/include/actables.h> #include <dev/acpica/acpivar.h> +#include <ia64/sgisn/sgisn_shub.h> + struct sgisn_shub_softc { struct sgisn_fwhub *sc_fwhub; device_t sc_dev; vm_paddr_t sc_membase; vm_size_t sc_memsize; + bus_addr_t sc_mmraddr; + bus_space_tag_t sc_tag; + bus_space_handle_t sc_hndl; u_int sc_domain; u_int sc_hubtype; /* SHub type (0=SHub1, 1=SHub2) */ u_int sc_nasid_mask; @@ -69,6 +74,8 @@ static int sgisn_shub_activate_resource( struct resource *); static int sgisn_shub_read_ivar(device_t, device_t, int, uintptr_t *); static int sgisn_shub_write_ivar(device_t, device_t, int, uintptr_t); +static struct resource *sgisn_shub_alloc_resource(device_t, device_t, int, + int *, u_long, u_long, u_long, u_int); /* * Bus interface definitions. @@ -83,7 +90,7 @@ static device_method_t sgisn_shub_method DEVMETHOD(bus_read_ivar, sgisn_shub_read_ivar), DEVMETHOD(bus_write_ivar, sgisn_shub_write_ivar), DEVMETHOD(bus_print_child, bus_generic_print_child), - DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), + DEVMETHOD(bus_alloc_resource, sgisn_shub_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, sgisn_shub_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), @@ -186,6 +193,7 @@ sgisn_shub_activate_resource(device_t de return (EDOOFUS); } +#if 0 static void sgisn_shub_dump_sn_info(struct ia64_sal_result *r) { @@ -205,6 +213,7 @@ sgisn_shub_dump_sn_info(struct ia64_sal_ (r->sal_result[1] >> 16) & 0xff); } +#endif static void sgisn_shub_identify_srat_cb(ACPI_SUBTABLE_HEADER *entry, void *arg) @@ -274,8 +283,10 @@ sgisn_shub_identify(driver_t *drv, devic if (r.sal_status != 0) return; +#if 0 if (bootverbose) sgisn_shub_dump_sn_info(&r); +#endif /* * The number of SHub ASICs is determined by the number of nodes @@ -388,6 +399,12 @@ sgisn_shub_attach(device_t dev) sc->sc_nasid = (sc->sc_membase >> sc->sc_nasid_shft) & sc->sc_nasid_mask; + sc->sc_mmraddr = (sc->sc_nasid << sc->sc_nasid_shft) | + (1UL << (sc->sc_nasid_shft - 3)) | + (((sc->sc_hubtype == 0) ? 1UL : 0UL) << 32); + sc->sc_tag = IA64_BUS_SPACE_MEM; + bus_space_map(sc->sc_tag, sc->sc_mmraddr, 1UL << 32, 0, &sc->sc_hndl); + if (bootverbose) device_printf(dev, "NASID=%#x\n", sc->sc_nasid); @@ -411,6 +428,13 @@ sgisn_shub_attach(device_t dev) for (wdgt = 0; wdgt < SGISN_HUB_NWIDGETS; wdgt++) sc->sc_fwhub->hub_widget[wdgt].wgt_hub = sc->sc_fwhub; + /* Create a child for the SAL-based console. */ + r = ia64_sal_entry(SAL_SGISN_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0); + if (r.sal_status == 0 && r.sal_result[0] == sc->sc_nasid) { + child = device_add_child(dev, "sncon", -1); + device_set_ivars(child, (void *)(uintptr_t)~0UL); + } + for (seg = 0; seg <= sc->sc_fwhub->hub_pci_maxseg; seg++) { for (bus = 0; bus <= sc->sc_fwhub->hub_pci_maxbus; bus++) { r = ia64_sal_entry(SAL_SGISN_IOBUS_INFO, seg, bus, @@ -456,3 +480,13 @@ sgisn_shub_write_ivar(device_t dev, devi return (ENOENT); } + +static struct resource * +sgisn_shub_alloc_resource(device_t dev, device_t child, int type, int *rid, + u_long start, u_long end, u_long count, u_int flags) +{ + struct resource *res; + + res = bus_alloc_resource(dev, type, rid, start, end, count, flags); + return (res); +} Added: projects/altix/sys/ia64/sgisn/sgisn_shub.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/altix/sys/ia64/sgisn/sgisn_shub.h Sun Apr 24 17:25:50 2011 (r220995) @@ -0,0 +1,51 @@ +/*- + * Copyright (c) 2011 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _IA64_SGISN_SHUB_H_ +#define _IA64_SGISN_SHUB_H_ + +#define SHUB_MMR_SIZE (1 << 32) + +#define SHUB_MMR_IPI 0x10000380 +#define SHUB_MMR_RTC1_ICFG 0x10001480 +#define SHUB_MMR_RTC1_IENA 0x10001500 +#define SHUB_MMR_RTC2_ICFG 0x10001580 +#define SHUB_MMR_RTC2_IENA 0x10001600 +#define SHUB_MMR_RTC3_ICFG 0x10001680 +#define SHUB_MMR_RTC3_IENA 0x10001700 +#define SHUB_MMR_EVENT 0x10010000 +#define SHUB_MMR_IPI_ACC 0x10060480 +#define SHUB_MMR_ID 0x10060580 +#define SHUB_MMR_PTC_CFG0 0x101a0000 +#define SHUB_MMR_PTC_CFG1 0x101a0080 +#define SHUB_MMR_RTC 0x101c0000 +#define SHUB_MMR_PIO_WSTAT0 0x20070200 +#define SHUB_MMR_PIO_WSTAT1 0x20070280 +#define SHUB_MMR_PTC 0x70000000 + +#endif /* _IA64_SGISN_SHUB_H_ */
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