Date: Sat, 24 Oct 2015 19:39:41 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r289887 - in head/sys/arm: arm include Message-ID: <201510241939.t9OJdfEh039673@repo.freebsd.org>
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Author: ian Date: Sat Oct 24 19:39:41 2015 New Revision: 289887 URL: https://svnweb.freebsd.org/changeset/base/289887 Log: Rename dcache_dma_preread() to dcache_inv_poc_dma() to make it clear that it is a dcache invalidate to point of coherency just like dcache_inv_poc(), but a slightly different version specific to dma operations. Elaborate the comment about how and why it's different. Modified: head/sys/arm/arm/busdma_machdep-v6.c head/sys/arm/include/cpu-v6.h Modified: head/sys/arm/arm/busdma_machdep-v6.c ============================================================================== --- head/sys/arm/arm/busdma_machdep-v6.c Sat Oct 24 19:38:06 2015 (r289886) +++ head/sys/arm/arm/busdma_machdep-v6.c Sat Oct 24 19:39:41 2015 (r289887) @@ -1284,7 +1284,7 @@ dma_preread_safe(vm_offset_t va, vm_padd if ((va + size) & cpuinfo.dcache_line_mask) dcache_wb_poc(va + size, pa + size, 1); - dcache_dma_preread(va, pa, size); + dcache_inv_poc_dma(va, pa, size); } static void @@ -1406,7 +1406,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus if ((op & BUS_DMASYNC_PREREAD) && !(op & BUS_DMASYNC_PREWRITE)) { bpage = STAILQ_FIRST(&map->bpages); while (bpage != NULL) { - dcache_dma_preread(bpage->vaddr, bpage->busaddr, + dcache_inv_poc_dma(bpage->vaddr, bpage->busaddr, bpage->datacount); bpage = STAILQ_NEXT(bpage, links); } Modified: head/sys/arm/include/cpu-v6.h ============================================================================== --- head/sys/arm/include/cpu-v6.h Sat Oct 24 19:38:06 2015 (r289886) +++ head/sys/arm/include/cpu-v6.h Sat Oct 24 19:39:41 2015 (r289887) @@ -471,15 +471,17 @@ dcache_inv_poc(vm_offset_t va, vm_paddr_ } /* - * Discard D-cache lines to PoC, prior to overwrite by DMA engine + * Discard D-cache lines to PoC, prior to overwrite by DMA engine. * - * Invalidate caches, discarding data in dirty lines. This is useful - * if the memory is about to be overwritten, e.g. by a DMA engine. - * Invalidate caches from innermost to outermost to follow the flow - * of dirty cachelines. + * Normal invalidation does L2 then L1 to ensure that stale data from L2 doesn't + * flow into L1 while invalidating. This routine is intended to be used only + * when invalidating a buffer before a DMA operation loads new data into memory. + * The concern in this case is that dirty lines are not evicted to main memory, + * overwriting the DMA data. For that reason, the L1 is done first to ensure + * that an evicted L1 line doesn't flow to L2 after the L2 has been cleaned. */ static __inline void -dcache_dma_preread(vm_offset_t va, vm_paddr_t pa, vm_size_t size) +dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size) { vm_offset_t eva = va + size;
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