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Date:      Sat, 2 Mar 2019 20:59:18 +0000 (UTC)
From:      Justin Hibbits <jhibbits@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r344729 - head/sys/powerpc/booke
Message-ID:  <201903022059.x22KxIDJ017837@repo.freebsd.org>

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Author: jhibbits
Date: Sat Mar  2 20:59:18 2019
New Revision: 344729
URL: https://svnweb.freebsd.org/changeset/base/344729

Log:
  powerpc/booke: Depessimize MAS register updates even more
  
  Remove isyncs between MAS register updates in the TLB miss handler, since
  it's only needed before the TLB update instructions.

Modified:
  head/sys/powerpc/booke/locore.S
  head/sys/powerpc/booke/trap_subr.S

Modified: head/sys/powerpc/booke/locore.S
==============================================================================
--- head/sys/powerpc/booke/locore.S	Sat Mar  2 20:58:51 2019	(r344728)
+++ head/sys/powerpc/booke/locore.S	Sat Mar  2 20:59:18 2019	(r344729)
@@ -252,6 +252,7 @@ __start:
 	isync
 	bl	zero_mas7
 	bl	zero_mas8
+	isync
 	tlbwe
 	isync
 	msync
@@ -505,6 +506,7 @@ bp_kernload:
 	isync
 	bl	zero_mas7
 	bl	zero_mas8
+	isync
 	tlbwe
 	isync
 	msync
@@ -695,6 +697,7 @@ tlb1_temp_mapping_as1:
 	bl	zero_mas7
 	bl	zero_mas8
 	mtlr	%r3
+	isync
 	tlbwe
 	isync
 	msync
@@ -742,7 +745,6 @@ zero_mas7:
 
 	li	%r20, 0
 	mtspr	SPR_MAS7, %r20
-	isync
 1:
 	blr
 
@@ -759,7 +761,6 @@ zero_mas8:
 1:
 	li	%r20, 0
 	mtspr	SPR_MAS8, %r20
-	isync
 	blr
 #endif
 

Modified: head/sys/powerpc/booke/trap_subr.S
==============================================================================
--- head/sys/powerpc/booke/trap_subr.S	Sat Mar  2 20:58:51 2019	(r344728)
+++ head/sys/powerpc/booke/trap_subr.S	Sat Mar  2 20:59:18 2019	(r344729)
@@ -761,17 +761,14 @@ search_failed:
 
 	/* Load MAS registers. */
 	mtspr	SPR_MAS0, %r29
-	isync
 	mtspr	SPR_MAS1, %r28
-	isync
 	mtspr	SPR_MAS2, %r27
-	isync
 	mtspr	SPR_MAS3, %r23
-	isync
 
 	bl	zero_mas7
 	bl	zero_mas8
 
+	isync
 	tlbwe
 	msync
 	isync
@@ -906,20 +903,16 @@ tlb_fill_entry:
 
 	/* Load MAS registers. */
 	mtspr	SPR_MAS0, %r29
-	isync
 	mtspr	SPR_MAS1, %r28
-	isync
 	mtspr	SPR_MAS2, %r27
-	isync
 	mtspr	SPR_MAS3, %r22
-	isync
 	mtspr	SPR_MAS7, %r23
-	isync
 
 	mflr	%r21
 	bl	zero_mas8
 	mtlr	%r21
 
+	isync
 	tlbwe
 	isync
 	msync



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