Date: Sat, 19 Jul 1997 22:24:28 -0600 From: Steve Passe <smp@csn.net> To: Bruce Evans <bde@zeta.org.au> Cc: current@FreeBSD.ORG, smp@FreeBSD.ORG Subject: Re: INT priorities Message-ID: <199707200424.WAA28515@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Sun, 20 Jul 1997 14:03:37 %2B1000." <199707200403.OAA23396@godzilla.zeta.org.au>
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Bruce, > The (non-SMP) kernel doesn't really care. It uses spl priorities > for essentially everything except fast interrupt handlers. For fast > interrupt handlers, the priorities only matter for interrupts that > arrive concurrently. I guess I should give a little background: The APIC provides 16 different priority levels for handling INTs. Because they are handled as messages, and each level has a 2 deep fifo, ideally we want at most 2 INTs assigned per level to avoid "message bounce". Because the timer and possibly other INTs can occur on non-standard IRQ #s, we can't compile in values for them. They can only be determined at run time. Another factor is that the APIC doesn't have 1 mask register like the 8259. Instead its an individual bit in a per-source register set, ie the 24 possible INTs sources are masked across 24 different registers. So keeping a bitmask in imen, and the bitmasks in the isa dev struct is of little use. Its actually counter-productive as many operations require a search of the mask for the particular bit of interest. It would be much better to keep INTs organized as logical INT #s, and use the # as an index into various tables, registers, etc. Given the need to reorganize INTs for the above reasons we might as well put a little thought into what goes where. -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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