Date: Thu, 12 Sep 1996 05:30:50 +0900 From: KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp> To: bde@zeta.org.au Cc: dg@Root.COM, kato@eclogite.eps.nagoya-u.ac.jp, current@FreeBSD.org Subject: Re: patch for Cyrix/Ti 486SLC/DLC CPU bug Message-ID: <199609112030.FAA04971@marble.eps.nagoya-u.ac.jp> In-Reply-To: Your message of "Thu, 12 Sep 1996 05:15:00 %2B1000" References: <199609111915.FAA08571@godzilla.zeta.org.au>
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On Thu, 12 Sep 1996 05:15:00 +1000, Bruce Evans <bde@zeta.org.au> said:
> which loads from %cr0. I guess the problem is in the non-386 case of
> pmap_update_{1,2}pg(). The magic .byte's are a bad way of writing
> `invlpg' (even gas understands this).
Oops! I misunderstood i486 instruction. `0x0f 0x01 0x38' is not
LMSW, that is not paging related register (except PG bit), but
INVLPG. Please read LMSW in my mails as INVLPG.
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KATO Takenori <kato@eclogite.eps.nagoya-u.ac.jp>
Dept. Earth Planet. Sci., Nagoya Univ., Nagoya, 464-01, Japan
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