Date: Mon, 9 Mar 2015 14:42:26 +0000 (UTC) From: Ian Lepore <ian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279810 - head/sys/arm/arm Message-ID: <201503091442.t29EgQlq051906@svn.freebsd.org>
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Author: ian Date: Mon Mar 9 14:42:25 2015 New Revision: 279810 URL: https://svnweb.freebsd.org/changeset/base/279810 Log: Clean data cache before instruction cache in armv7_icache_sync_range(). Also ensure dsb precedes isb in all icache maintenance routines (first do a data sync, then stall the instruction stream until it finishes). Submitted by: Michal Meloun Modified: head/sys/arm/arm/cpufunc_asm_armv7.S Modified: head/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S Mon Mar 9 14:01:35 2015 (r279809) +++ head/sys/arm/arm/cpufunc_asm_armv7.S Mon Mar 9 14:42:25 2015 (r279810) @@ -247,8 +247,8 @@ ENTRY(armv7_idcache_wbinv_range) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_id_wbinv_next - isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ + isb /* instruction synchronization barrier */ RET END(armv7_idcache_wbinv_range) @@ -258,8 +258,8 @@ ENTRY_NP(armv7_icache_sync_all) #else mcr CP15_ICIALLU #endif - isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ + isb /* instruction synchronization barrier */ RET END(armv7_icache_sync_all) @@ -267,13 +267,13 @@ ENTRY_NP(armv7_icache_sync_range) ldr ip, .Larmv7_icache_line_size ldr ip, [ip] .Larmv7_sync_next: - mcr CP15_ICIMVAU(r0) mcr CP15_DCCMVAC(r0) + mcr CP15_ICIMVAU(r0) add r0, r0, ip subs r1, r1, ip bhi .Larmv7_sync_next - isb /* instruction synchronization barrier */ dsb /* data synchronization barrier */ + isb /* instruction synchronization barrier */ RET END(armv7_icache_sync_range)
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