Date: Sun, 13 Oct 2002 12:04:25 -0700 From: Terry Lambert <tlambert2@mindspring.com> To: ticso@cicely.de Cc: "M. Warner Losh" <imp@bsdimp.com>, hch@infradead.org, wes@softweyr.com, dillon@apollo.backplane.com, vova@sw.ru, nate@root.org, arch@FreeBSD.org Subject: Re: Database indexes and ram Message-ID: <3DA9C3B9.E78BBFE6@mindspring.com> References: <3DA954CF.98B0891A@mindspring.com> <20021013.060851.113437955.imp@bsdimp.com> <3DA9B4A8.194A02FC@mindspring.com> <20021013.120847.31902907.imp@bsdimp.com> <20021013181633.GB34517@cicely8.cicely.de>
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Bernd Walter wrote: > Of course they can do. > It's just a matter if the card and the board support 2 address cycles. > Or if the board can map the pci reachable space - as alphas can do. The question is whether you can say reliably that all cards that will be sharing cached data space can do this, or whether you will have to bounce the data to below 4G. If you can't *know*, then to ensure operation, you *must* bounce the data to proactively guarantee that the physical address will be in range of the card's DMA engine. Among other things, this means recognizing a 32 bit card in a 64 bit slot, and a 64 bit card in a 32 bit slot, and a 64 bit card in a 64 bit slot, but which has only 32 bits worth of electrical connector on the physical card. If you can guarantee that, then you can do it without bouncing. Can you do that? -- Terry To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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