Date: Tue, 11 Mar 1997 12:12:22 +0100 (MET) From: Luigi Rizzo <luigi@labinfo.iet.unipi.it> To: dg@root.com Cc: msmith@atrad.adelaide.edu.au, bde@zeta.org.au, bag@sinbin.demos.su, hackers@FreeBSD.ORG Subject: Re: performance (was: 100 Mb/s cards) Message-ID: <199703111112.MAA29471@labinfo.iet.unipi.it> In-Reply-To: <199703111024.CAA19472@root.com> from "David Greenman" at Mar 11, 97 02:23:42 am
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> >probably necessary (so that the ethernet header goes into a separate > >mbuf). I have no idea if any of our drivers does this, but probably it > >would be a nice thing to have. ... > Alpha. Both the de and fxp drivers DMA the packet with the ethernet header > aligned on a 32bit boundry, which means that the packet minus the ether > header is not 32bit aligned (only 16bit alignment). Due to the architecture > of the DC21x4x, it's not possible to work around this. It is possible to > use different alignment with the Pro/100B chip (82557), but I don't currently > do that in the driver - it was easier not to bother. I might change this > in the future. I just checked the data sheets of the 21140; too bad, it appears that the 21140 can use unaligned buffers on the TRANSMIT side but not on the receive side. As other controllers, a packet can be split into multiple buffers though, so that a sensible (and sufficiently general) fix would be to store the ethernet header (12 bytes) in the first mbuf, and the body of the packet (starting with the IP header) in the following mbuf cluster. For busy 100 Mbit-based systems this might result in a major reduction in the memory bandwidth consumed by the network. Luigi -----------------------------+-------------------------------------- Luigi Rizzo | Dip. di Ingegneria dell'Informazione email: luigi@iet.unipi.it | Universita' di Pisa tel: +39-50-568533 | via Diotisalvi 2, 56126 PISA (Italy) fax: +39-50-568522 | http://www.iet.unipi.it/~luigi/ _____________________________|______________________________________
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