Date: Fri, 03 Jun 2005 14:49:17 -0700 From: Colin Percival <cperciva@freebsd.org> To: Matthew Dillon <dillon@apollo.backplane.com> Cc: freebsd-hackers@freebsd.org Subject: Re: Possible instruction pipelining problem between HT's on the same die ? Message-ID: <42A0D05D.8040809@freebsd.org> In-Reply-To: <200506032057.j53KvOFw062012@apollo.backplane.com> References: <200506032057.j53KvOFw062012@apollo.backplane.com>
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Matthew Dillon wrote: > I'm even more confused because this bug is occuring between two logical > cpus on the same physical die. Is write ordering not guarenteed with > respect to the other logical cpu? Can one logical cpu prefetch data > early then then becomes obsolete by the time the instruction is actually > run? My understanding is that the circuits which detect if a speculative read needs to be re-done work only with the logical addresses. As such, you can get bogus data from speculative reads even between two threads within the same core if you don't use proper fencing instructions. But I may be completely confused here -- all the interesting details are in NDA'ed manuals which I can't get access to. :-( Colin Percival
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