Date: Mon, 14 Oct 2013 23:57:12 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r256482 - head/sys/mips/atheros Message-ID: <201310142357.r9ENvC6P046324@svn.freebsd.org>
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Author: adrian Date: Mon Oct 14 23:57:12 2013 New Revision: 256482 URL: http://svnweb.freebsd.org/changeset/base/256482 Log: Add register definitions for the AR933x SoC GMAC (ie, ethernet MAC) control block. The GMAC configuration block allows for some configuration of how the GMAC0 (ie, arge0) port is connected to the on-board switch (if indeed there is one.) It both can be pushed into the on-board switch; it could also be torn out and exposed via an external MII (and that operational mode is also controllable.) Obtained from: Linux/OpenWRT Modified: head/sys/mips/atheros/ar933xreg.h Modified: head/sys/mips/atheros/ar933xreg.h ============================================================================== --- head/sys/mips/atheros/ar933xreg.h Mon Oct 14 23:56:38 2013 (r256481) +++ head/sys/mips/atheros/ar933xreg.h Mon Oct 14 23:57:12 2013 (r256482) @@ -38,6 +38,24 @@ #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) #define AR933X_UART_SIZE 0x14 + +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 + +#define AR933X_GMAC_REG_ETH_CFG (AR933X_GMAC_BASE + 0x00) + +#define AR933X_ETH_CFG_RGMII_GE0 (1 << 0) +#define AR933X_ETH_CFG_MII_GE0 (1 << 1) +#define AR933X_ETH_CFG_GMII_GE0 (1 << 2) +#define AR933X_ETH_CFG_MII_GE0_MASTER (1 << 3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE (1 << 4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN (1 << 5) +#define AR933X_ETH_CFG_SW_PHY_SWAP (1 << 7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP (1 << 8) +#define AR933X_ETH_CFG_RMII_GE0 (1 << 9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 (1 << 10) + #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) #define AR933X_WMAC_SIZE 0x20000 #define AR933X_EHCI_BASE 0x1b000000
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