Date: Wed, 27 Oct 2010 22:59:34 +0200 From: Milan Obuch <freebsd-arm@dino.sk> To: Rafal Jaworowski <raj@semihalf.com> Cc: freebsd-arm@freebsd.org Subject: Re: Guruplug Server Plus working to some extent... [mge1 problem SOLVED] Message-ID: <201010272259.36319.freebsd-arm@dino.sk> In-Reply-To: <7C9980A5-1812-4162-82E0-2374EACFA24A@semihalf.com> References: <201010202309.40148.freebsd-arm@dino.sk> <201010271656.53245.freebsd-arm@dino.sk> <7C9980A5-1812-4162-82E0-2374EACFA24A@semihalf.com>
next in thread | previous in thread | raw e-mail | index | archive | help
--Boundary-00=_3KJyMswB+YCmZAJ
Content-Type: Text/Plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
On Wednesday 27 October 2010 18:44:23 Rafal Jaworowski wrote:
> On 2010-10-27, at 16:56, Milan Obuch wrote:
> > On Tuesday 26 October 2010 23:19:59 Kristof Provost wrote:
[snip]
> >> In any case, what I wanted to see is already printed in the boot log.
> >> Both mge interfaces are using the correct memory locatins (0xf1076000
> >> for mge1) and the correct PHY numbers.
> >>
> >> Did you statically configure the mac addresses in the DTS for this boot?
> >
> > Yes. Without that, ether addres did not initialize and needs to be set
> > manually.
> >
> > However, after looking over older mails again and trying to look at it
> > from the other side, I found the reason. I am going to write a follow-up
> > explaining the whole issue and how succesfully solved the problem...
> > please wait a bit, something unrelated needs to be done now...
>
> Have you got your MPP settings sorted out correctly? The second GE unit
> connections are multiplexed with other functions of the SOC and won't work
> without proper set-up, see the hardware spec and the description of MPP
> bindings in the DTS sys/boot/fdt/dts/bindings-mpp.txt
>
Exactly this was the reason, however file you mentioned was not that helpfull
for me... but looking at dts for OpenRD client and hardware spec for 88F6281 I
got the idea and after looking a bit at linux sources for guruplug server I
modified my dts and this also explain why frames could be received before and
not sent - all pins set as gpio are inputs in a way, thus reading worked, but
controller output was not connected to phy, so in effect tcpdump saw input and
frames to be sent, but tha's on chip, and they did not get out of chip.
That's it for theory, and now some summary - I am attaching patches I used for
Guruplug to work, collected from older mails. Patch for mvwin.h and ehci_mv.c
are necessary for USB to work correctly. I mentioned them in my first mail
dated October 20, 2010, original source is mail from Johny Mattsson dated
September 18, 2010. Patch for if_mge.c makes it unnecessary to specify phy
handle in dts and probes them automatically, originally in mail from Norikatsu
Shigemura dated June 20, 2010. I modified it a bit to account for changes in
sources in between.
For kernel config see my first mail. New dts is attached here.
One issue still remains - mge1 has no unique ether address, all-zero is set
upon reboot unless explicitly set in dts. This is small issue for me, need not
be resolved urgently.
A bit more important problem is gpio - I have line
gpio0: <Marvell Integrated GPIO Controller> mem 0xf1010100-0xf101011f irq
35,36,37,38,39,40,41 on simplebus0
in boot log/dmesg output, yet there is no /dev/gpio file of similar usable
with gpioctl. Some LEDs are connected to gpio pins, some pins are accessible
through u-snap connector and thus are interesting for I/O... Any hint here?
Regards,
Milan
--Boundary-00=_3KJyMswB+YCmZAJ
Content-Type: text/plain; charset="iso-8859-1";
name="patch-sys::arm::mv::mvwin.h"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="patch-sys::arm::mv::mvwin.h"
--- sys/arm/mv/mvwin.h.orig 2010-06-13 15:28:53.000000000 +0200
+++ sys/arm/mv/mvwin.h 2010-10-18 23:20:27.000000000 +0200
@@ -138,8 +138,8 @@
#define MV_WIN_CESA_ATTR 0
#endif
-#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0)
-#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4)
+#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320)
+#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324)
#define MV_WIN_USB_MAX 4
#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
--Boundary-00=_3KJyMswB+YCmZAJ
Content-Type: text/plain; charset="iso-8859-1";
name="patch-sys::dev::usb::controller::ehci_mv.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="patch-sys::dev::usb::controller::ehci_mv.c"
--- sys/dev/usb/controller/ehci_mv.c.orig 2010-06-13 15:28:53.000000000 +0200
+++ sys/dev/usb/controller/ehci_mv.c 2010-10-18 23:23:08.000000000 +0200
@@ -96,6 +96,7 @@
#define USB_BRIDGE_INTR_CAUSE 0x210
#define USB_BRIDGE_INTR_MASK 0x214
+#define USB_BRIDGE_ERR_ADDR 0x21C
#define MV_USB_ADDR_DECODE_ERR (1 << 0)
#define MV_USB_HOST_UNDERFLOW (1 << 1)
@@ -360,6 +361,21 @@
printf("IRQ ERR: Unknown error\n");
EWRITE4(sc, USB_BRIDGE_INTR_CAUSE, 0);
+
+ /*
+ * In case of an address decode error, we must read from
+ * the USB_BRIDGE_ERR_ADDR register to clear it to allow
+ * the controller to latch a new address in next time this
+ * error occurs. If we don't read it, we get the interrupt
+ * reissued ad infinitum, even though we have cleared the
+ * interrupt cause.
+ */
+ if (cause & MV_USB_ADDR_DECODE_ERR)
+ {
+ unsigned erraddr = EREAD4(sc, USB_BRIDGE_ERR_ADDR);
+ printf("IRQ ERR: USB Bridge Error Address: 0x%08x\n",
+ erraddr);
+ }
}
return (FILTER_HANDLED);
}
--Boundary-00=_3KJyMswB+YCmZAJ
Content-Type: text/plain; charset="iso-8859-1";
name="patch-sys::dev::mge::if_mge.c"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="patch-sys::dev::mge::if_mge.c"
--- sys/dev/mge/if_mge.c.orig 2010-10-15 16:52:11.000000000 +0200
+++ sys/dev/mge/if_mge.c 2010-10-27 08:53:31.000000000 +0200
@@ -626,7 +626,6 @@
mge_attach(device_t dev)
{
struct mge_softc *sc;
- struct mii_softc *miisc;
struct ifnet *ifp;
uint8_t hwaddr[ETHER_ADDR_LEN];
int i, error, phy;
@@ -643,7 +642,7 @@
/* Get phy address from fdt */
if (fdt_get_phyaddr(sc->node, &phy) != 0)
- return (ENXIO);
+ phy = -1;
/* Initialize mutexes */
mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
@@ -674,6 +673,9 @@
sc->tx_ic_time = 768;
mge_add_sysctls(sc);
+ if (phy == -1)
+ phy = MGE_READ(sc, MGE_REG_PHYDEV);
+
/* Allocate network interface */
ifp = sc->ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
@@ -717,8 +719,7 @@
sc->mii = device_get_softc(sc->miibus);
/* Tell the MAC where to find the PHY so autoneg works */
- miisc = LIST_FIRST(&sc->mii->mii_phys);
- MGE_WRITE(sc, MGE_REG_PHYDEV, miisc->mii_phy);
+ MGE_WRITE(sc, MGE_REG_PHYDEV, phy);
/* Attach interrupt handlers */
for (i = 0; i < 2; ++i) {
@@ -868,7 +869,7 @@
struct mge_softc *sc = arg;
struct mge_desc_wrapper *dw;
volatile uint32_t reg_val;
- int i, count;
+ int i;
MGE_GLOBAL_LOCK_ASSERT(sc);
@@ -949,17 +950,6 @@
reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
reg_val |= PORT_SERIAL_ENABLE;
MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
- count = 0x100000;
- for (;;) {
- reg_val = MGE_READ(sc, MGE_PORT_STATUS);
- if (reg_val & MGE_STATUS_LINKUP)
- break;
- DELAY(100);
- if (--count == 0) {
- if_printf(sc->ifp, "Timeout on link-up\n");
- break;
- }
- }
/* Setup interrupts coalescing */
mge_set_rxic(sc);
@@ -1484,8 +1474,8 @@
MGE_TRANSMIT_LOCK_ASSERT(sc);
- if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
- IFF_DRV_RUNNING)
+ if (IFM_SUBTYPE(sc->mii->mii_media_active) == IFM_NONE ||
+ (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
return;
for (;;) {
--Boundary-00=_3KJyMswB+YCmZAJ
Content-Type: text/plain;
charset="iso-8859-1";
name="guruplugplus.dts"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="guruplugplus.dts"
/*
* Copyright (c) 2010 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Semihalf under sponsorship from
* the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Marvell SheevaPlug Device Tree Source.
* *** modified for Guruplug server plus ***
*
* $FreeBSD$
*/
/dts-v1/;
/ {
model = "mrvl,GuruPlugPlus";
compatible = "GuruPlugPlus";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
mpp = &MPP;
serial0 = &serial0;
serial1 = &serial1;
soc = &SOC;
sram = &SRAM;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "ARM,88FR131";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x4000>; // L1, 16K
i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x20000000>; // 512M at 0x0
};
localbus@f1000000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "mrvl,lbc";
/* This reflects CPU decode windows setup. */
ranges = <0x0 0x0f 0xf9300000 0x00100000
0x1 0x1e 0xfa000000 0x00100000
0x2 0x1d 0xfa100000 0x02000000
0x3 0x1b 0xfc100000 0x00000400>;
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
led@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "led";
reg = <0x1 0x0 0x00100000>;
};
nor@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x2 0x0 0x02000000>;
bank-width = <2>;
device-width = <1>;
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x3 0x0 0x00100000>;
bank-width = <2>;
device-width = <1>;
};
};
SOC: soc88f6281@f1000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x0 0xf1000000 0x00100000>;
bus-frequency = <0>;
PIC: pic@20200 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x20200 0x3c>;
compatible = "mrvl,pic";
};
timer@20300 {
compatible = "mrvl,timer";
reg = <0x20300 0x30>;
interrupts = <1>;
interrupt-parent = <&PIC>;
mrvl,has-wdt;
};
MPP: mpp@10000 {
#pin-cells = <2>;
compatible = "mrvl,mpp";
reg = <0x10000 0x34>;
pin-count = <50>;
pin-map = <
0 1 /* MPP[0]: NF_IO[2] */
1 1 /* MPP[1]: NF_IO[3] */
2 1 /* MPP[2]: NF_IO[4] */
3 1 /* MPP[3]: NF_IO[5] */
4 1 /* MPP[4]: NF_IO[6] */
5 1 /* MPP[5]: NF_IO[7] */
6 1 /* MPP[6]: SYSRST_OUTn */
7 0 /* MPP[7]: GPO[7] */
8 1 /* MPP[8]: TW_SDA */
9 1 /* MPP[9]: TW_SCK */
10 3 /* MPP[10]: UA0_TXD */
11 3 /* MPP[11]: UA0_RXD */
12 1 /* MPP[12]: SD_CLK */
13 1 /* MPP[13]: SD_CMD */
14 1 /* MPP[14]: SD_D[0] */
15 1 /* MPP[15]: SD_D[1] */
16 1 /* MPP[16]: SD_D[2] */
17 1 /* MPP[17]: SD_D[3] */
18 1 /* MPP[18]: NF_IO[0] */
19 1 /* MPP[19]: NF_IO[1] */
20 3 /* MPP[20]: GE1[0] */
21 3 /* MPP[21]: GE1[1] */
22 3 /* MPP[22]: GE1[2] */
23 3 /* MPP[23]: GE1[3] */
24 3 /* MPP[24]: GE1[4] */
25 3 /* MPP[25]: GE1[5] */
26 3 /* MPP[26]: GE1[6] */
27 3 /* MPP[27]: GE1[7] */
28 0 /* MPP[28]: GPIO[28] */
29 1 /* MPP[29]: TSMP[9] */
30 3 /* MPP[30]: GE1[10] */
31 3 /* MPP[31]: GE1[11] */
32 3 /* MPP[32]: GE1[12] */
33 3 /* MPP[33]: GE1[13] */
34 0 /* MPP[34]: GPIO[34] */
35 2 /* MPP[35]: TDM_CH0_TX_QL */
36 2 /* MPP[36]: TDM_SPI_CS1 */
37 2 /* MPP[37]: TDM_CH2_TX_QL */
38 0 /* MPP[38]: GPIO[38] */
39 0 /* MPP[39]: GPIO[39] */
40 0 /* MPP[40]: GPIO[40] */
41 0 /* MPP[41]: GPIO[41] */
42 0 /* MPP[42]: GPIO[42] */
43 0 /* MPP[43]: GPIO[43] */
44 4 /* MPP[44]: AU_EXTCLK */
45 2 /* MPP[45]: TDM_PCLK */
46 0 /* MPP[46]: GPIO[46] */
47 0 /* MPP[47]: GPIO[47] */
48 0 /* MPP[48]: GPIO[48] */
49 0 /* MPP[49]: GPIO[49] */
>;
};
GPIO: gpio@10100 {
#gpio-cells = <3>;
compatible = "mrvl,gpio";
reg = <0x10100 0x20>;
gpio-controller;
interrupts = <35 36 37 38 39 40 41>;
interrupt-parent = <&PIC>;
};
rtc@10300 {
compatible = "mrvl,rtc";
reg = <0x10300 0x08>;
};
twsi@11000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mrvl,twsi";
reg = <0x11000 0x20>;
interrupts = <43>;
interrupt-parent = <&PIC>;
};
enet0: ethernet@72000 {
#address-cells = <1>;
#size-cells = <1>;
model = "V2";
compatible = "mrvl,ge";
reg = <0x72000 0x2000>;
ranges = <0x0 0x72000 0x2000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <12 13 14 11 46>;
interrupt-parent = <&PIC>;
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mrvl,mdio";
};
};
enet1: ethernet@76000 {
#address-cells = <1>;
#size-cells = <1>;
model = "V2";
compatible = "mrvl,ge";
reg = <0x76000 0x2000>;
ranges = <0x0 0x76000 0x2000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <16 17 18 15 47>;
interrupt-parent = <&PIC>;
mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mrvl,mdio";
};
};
serial0: serial@12000 {
compatible = "ns16550";
reg = <0x12000 0x20>;
reg-shift = <2>;
clock-frequency = <0>;
interrupts = <33>;
interrupt-parent = <&PIC>;
};
serial1: serial@12100 {
compatible = "ns16550";
reg = <0x12100 0x20>;
reg-shift = <2>;
clock-frequency = <0>;
interrupts = <34>;
interrupt-parent = <&PIC>;
};
crypto@30000 {
compatible = "mrvl,cesa";
reg = <0x30000 0x10000>;
interrupts = <22>;
interrupt-parent = <&PIC>;
};
usb@50000 {
compatible = "mrvl,usb-ehci", "usb-ehci";
reg = <0x50000 0x1000>;
interrupts = <48 19>;
interrupt-parent = <&PIC>;
};
xor@60000 {
compatible = "mrvl,xor";
reg = <0x60000 0x1000>;
interrupts = <5 6 7 8>;
interrupt-parent = <&PIC>;
};
sata@80000 {
compatible = "mrvl,sata";
reg = <0x80000 0x6000>;
interrupts = <21>;
interrupt-parent = <&PIC>;
};
};
SRAM: sram@fd000000 {
compatible = "mrvl,cesa-sram";
reg = <0xfd000000 0x00100000>;
};
chosen {
stdin = "serial0";
stdout = "serial0";
};
};
--Boundary-00=_3KJyMswB+YCmZAJ--
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201010272259.36319.freebsd-arm>