Date: Sun, 19 Oct 2014 21:38:59 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r273291 - in projects/bhyve_svm: sys/amd64/vmm sys/x86/include usr.sbin/bhyve Message-ID: <201410192138.s9JLcxtU077265@svn.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: neel Date: Sun Oct 19 21:38:58 2014 New Revision: 273291 URL: https://svnweb.freebsd.org/changeset/base/273291 Log: Don't advertise the "OS visible workarounds" feature in cpuid.80000001H:ECX. bhyve doesn't emulate the MSRs needed to support this feature at this time. Don't expose any model-specific RAS and performance monitoring features in cpuid leaf 80000007H. Emulate a few more MSRs for AMD: TSEG base address, TSEG address mask and BIOS signature and P-state related MSRs. This eliminates all the unimplemented MSRs accessed by Linux/x86_64 kernels 2.6.32, 3.10.0 and 3.17.0. Modified: projects/bhyve_svm/sys/amd64/vmm/x86.c projects/bhyve_svm/sys/x86/include/specialreg.h projects/bhyve_svm/usr.sbin/bhyve/xmsr.c Modified: projects/bhyve_svm/sys/amd64/vmm/x86.c ============================================================================== --- projects/bhyve_svm/sys/amd64/vmm/x86.c Sun Oct 19 21:16:24 2014 (r273290) +++ projects/bhyve_svm/sys/amd64/vmm/x86.c Sun Oct 19 21:38:58 2014 (r273291) @@ -174,6 +174,9 @@ x86_emulate_cpuid(struct vm *vm, int vcp /* NodeID MSR not available */ regs[2] &= ~AMDID2_NODE_ID; + /* Don't advertise the OS visible workaround feature */ + regs[2] &= ~AMDID2_OSVW; + /* * Hide rdtscp/ia32_tsc_aux until we know how * to deal with them. @@ -182,11 +185,25 @@ x86_emulate_cpuid(struct vm *vm, int vcp break; case CPUID_8000_0007: - cpuid_count(*eax, *ecx, regs); /* - * If the host TSCs are not synchronized across - * physical cpus then we cannot advertise an - * invariant tsc to a vcpu. + * AMD uses this leaf to advertise the processor's + * power monitoring and RAS capabilities. These + * features are hardware-specific and exposing + * them to a guest doesn't make a lot of sense. + * + * Intel uses this leaf only to advertise the + * "Invariant TSC" feature with all other bits + * being reserved (set to zero). + */ + regs[0] = 0; + regs[1] = 0; + regs[2] = 0; + regs[3] = 0; + + /* + * "Invariant TSC" can be advertised to the guest if: + * - host TSC frequency is invariant + * - host TSCs are synchronized across physical cpus * * XXX This still falls short because the vcpu * can observe the TSC moving backwards as it @@ -194,8 +211,8 @@ x86_emulate_cpuid(struct vm *vm, int vcp * it should discourage the guest from using the * TSC to keep track of time. */ - if (!smp_tsc) - regs[3] &= ~AMDPM_TSC_INVARIANT; + if (tsc_is_invariant && smp_tsc) + regs[3] |= AMDPM_TSC_INVARIANT; break; case CPUID_0000_0001: Modified: projects/bhyve_svm/sys/x86/include/specialreg.h ============================================================================== --- projects/bhyve_svm/sys/x86/include/specialreg.h Sun Oct 19 21:16:24 2014 (r273290) +++ projects/bhyve_svm/sys/x86/include/specialreg.h Sun Oct 19 21:38:58 2014 (r273291) @@ -785,6 +785,12 @@ #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ +#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ +#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ +#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ +#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ +#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ +#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044 Modified: projects/bhyve_svm/usr.sbin/bhyve/xmsr.c ============================================================================== --- projects/bhyve_svm/usr.sbin/bhyve/xmsr.c Sun Oct 19 21:16:24 2014 (r273290) +++ projects/bhyve_svm/usr.sbin/bhyve/xmsr.c Sun Oct 19 21:38:58 2014 (r273291) @@ -87,6 +87,10 @@ emulate_wrmsr(struct vmctx *ctx, int vcp /* Ignore writes to the PerfCtr MSRs */ return (0); + case MSR_P_STATE_CONTROL: + /* Ignore write to change the P-state */ + return (0); + default: break; } @@ -122,6 +126,9 @@ emulate_rdmsr(struct vmctx *ctx, int vcp } } else if (cpu_vendor_amd) { switch (num) { + case MSR_BIOS_SIGN: + *val = 0; + break; case MSR_HWCR: /* * Bios and Kernel Developer's Guides for AMD Families @@ -161,7 +168,25 @@ emulate_rdmsr(struct vmctx *ctx, int vcp */ *val = 0; break; + + case MSR_SMM_ADDR: + case MSR_SMM_MASK: + /* + * Return the reset value defined in the AMD Bios and + * Kernel Developer's Guide. + */ + *val = 0; + break; + + case MSR_P_STATE_LIMIT: + case MSR_P_STATE_CONTROL: + case MSR_P_STATE_STATUS: + case MSR_P_STATE_CONFIG(0): /* P0 configuration */ + *val = 0; + break; + default: + error = -1; break; } } else {
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201410192138.s9JLcxtU077265>