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Date:      Sun, 28 Mar 2010 02:48:39 +0000 (UTC)
From:      Juli Mallett <jmallett@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r205787 - in user/jmallett/octeon/sys/mips: include mips
Message-ID:  <201003280248.o2S2mdEU076528@svn.freebsd.org>

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Author: jmallett
Date: Sun Mar 28 02:48:39 2010
New Revision: 205787
URL: http://svn.freebsd.org/changeset/base/205787

Log:
  o) Spell PAGE_SIZE as PAGE_SIZE not NBPG, etc.
  o) Expand some macros related to tlb.S.
  o) Make some page-related macros more consistent.

Modified:
  user/jmallett/octeon/sys/mips/include/cpu.h
  user/jmallett/octeon/sys/mips/include/param.h
  user/jmallett/octeon/sys/mips/include/pte.h
  user/jmallett/octeon/sys/mips/mips/exception.S
  user/jmallett/octeon/sys/mips/mips/genassym.c
  user/jmallett/octeon/sys/mips/mips/locore.S
  user/jmallett/octeon/sys/mips/mips/mp_machdep.c
  user/jmallett/octeon/sys/mips/mips/mpboot.S
  user/jmallett/octeon/sys/mips/mips/pmap.c
  user/jmallett/octeon/sys/mips/mips/support.S
  user/jmallett/octeon/sys/mips/mips/tlb.S
  user/jmallett/octeon/sys/mips/mips/trap.c
  user/jmallett/octeon/sys/mips/mips/vm_machdep.c

Modified: user/jmallett/octeon/sys/mips/include/cpu.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpu.h	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/include/cpu.h	Sun Mar 28 02:48:39 2010	(r205787)
@@ -516,16 +516,6 @@ extern int intr_nesting_level;
 			: "r" (func), "r" (arg0), "r" (arg1), "r" (arg2)  /* inputs */ \
 			: "$31", "$4", "$5", "$6");
 
-#define	MachSetPID			Mips_SetPID
-#define	MachTLBUpdate   		Mips_TLBUpdate
-#define	mips_TBIS			Mips_TLBFlushAddr
-#define	MIPS_TBIAP()			mips_TBIAP(num_tlbentries)
-#define	MachSetWIRED(index)		Mips_SetWIRED(index)
-#define	MachTLBFlush(count)		Mips_TLBFlush(count)
-#define	MachTLBGetPID(pid)		(pid = Mips_TLBGetPID())
-#define	MachTLBRead(tlbno, tlbp)	Mips_TLBRead(tlbno, tlbp)
-#define	MachFPTrap(sr, cause, pc)	MipsFPTrap(sr, cause, pc)
-
 /*
  * Enable realtime clock (always enabled).
  */

Modified: user/jmallett/octeon/sys/mips/include/param.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/param.h	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/include/param.h	Sun Mar 28 02:48:39 2010	(r205787)
@@ -102,10 +102,6 @@
 #define	CACHE_LINE_SHIFT	6
 #define	CACHE_LINE_SIZE		(1 << CACHE_LINE_SHIFT)
 
-#define	NBPG		4096		/* bytes/page */
-#define	PGOFSET		(NBPG-1)	/* byte offset into page */
-#define	PGSHIFT		12		/* LOG2(NBPG) */
-
 #define	PAGE_SHIFT	12		/* LOG2(PAGE_SIZE) */
 #define	PAGE_SIZE	(1<<PAGE_SHIFT) /* bytes/page */
 #define	PAGE_MASK	(PAGE_SIZE-1)
@@ -128,8 +124,8 @@
 #define	UPAGES			2
 
 /* pages ("clicks") (4096 bytes) to disk blocks */
-#define	ctod(x)		((x) << (PGSHIFT - DEV_BSHIFT))
-#define	dtoc(x)		((x) >> (PGSHIFT - DEV_BSHIFT))
+#define	ctod(x)		((x) << (PAGE_SHIFT - DEV_BSHIFT))
+#define	dtoc(x)		((x) >> (PAGE_SHIFT - DEV_BSHIFT))
 
 /*
  * Map a ``block device block'' to a file system block.
@@ -140,18 +136,18 @@
 #define	bdbtofsb(bn)	((bn) / (BLKDEV_IOSIZE/DEV_BSIZE))
 
 /*
- * Conversion macros
+ * Mach derived conversion macros
  */
-#define	mips_round_page(x)	((((unsigned long)(x)) + NBPG - 1) & ~(NBPG-1))
-#define	mips_trunc_page(x)	((unsigned long)(x) & ~(NBPG-1))
-#define	mips_btop(x)		((unsigned long)(x) >> PGSHIFT)
-#define	mips_ptob(x)		((unsigned long)(x) << PGSHIFT)
-#define	round_page		mips_round_page
-#define	trunc_page		mips_trunc_page
-#define	atop(x)			((unsigned long)(x) >> PAGE_SHIFT)
-#define	ptoa(x)			((unsigned long)(x) << PAGE_SHIFT)
+#define round_page(x)		(((unsigned long)(x) + PAGE_MASK) & ~PAGE_MASK)
+#define trunc_page(x)		((unsigned long)(x) & ~PAGE_MASK)
+
+#define atop(x)			((unsigned long)(x) >> PAGE_SHIFT)
+#define ptoa(x)			((unsigned long)(x) << PAGE_SHIFT)
+
+#define mips_btop(x)		((unsigned long)(x) >> PAGE_SHIFT)
+#define mips_ptob(x)		((unsigned long)(x) << PAGE_SHIFT)
 
-#define	pgtok(x)		((x) * (PAGE_SIZE / 1024))
+#define	pgtok(x)		((unsigned long)(x) * (PAGE_SIZE / 1024))
 
 #ifndef _KERNEL
 #define	DELAY(n)	{ register int N = (n); while (--N > 0); }

Modified: user/jmallett/octeon/sys/mips/include/pte.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/pte.h	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/include/pte.h	Sun Mar 28 02:48:39 2010	(r205787)
@@ -121,12 +121,11 @@ typedef pt_entry_t *pd_entry_t;
 
 #define	PTE_SHIFT	6
 #define	pfn_is_ext(x)	((x) & 0x3c000000)
-#define	vad_to_pfn(x)	(((unsigned)(x) >> PTE_SHIFT) & PTE_FRAME)
-#define	vad_to_pfn64(x)	((quad_t)(x) >> PTE_SHIFT) & PTE_FRAME)
+#define	vad_to_pfn(x)	(((vm_offset_t)(x) >> PTE_SHIFT) & PTE_FRAME)
 #define	pfn_to_vad(x)	(((x) & PTE_FRAME) << PTE_SHIFT)
 
 /* User virtual to pte offset in page table */
-#define	vad_to_pte_offset(adr)	(((adr) >> PGSHIFT) & (NPTEPG -1))
+#define	vad_to_pte_offset(adr)	(((adr) >> PAGE_SHIFT) & (NPTEPG -1))
 
 #define	mips_pg_v(entry)	((entry) & PTE_V)
 #define	mips_pg_wired(entry)	((entry) & PTE_WIRED)

Modified: user/jmallett/octeon/sys/mips/mips/exception.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/exception.S	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/exception.S	Sun Mar 28 02:48:39 2010	(r205787)
@@ -147,7 +147,7 @@ MipsDoTLBMiss:
 	PTR_L	k1, 0(k1)			#08: k1=seg entry
 	mfc0	k0, COP_0_BAD_VADDR		#09: k0=bad address (again)
 	beq	k1, zero, 2f			#0a: ==0 -- no page table
-	srl	k0, PGSHIFT - 2			#0b: k0=VPN (aka va>>10)
+	srl	k0, PAGE_SHIFT - 2			#0b: k0=VPN (aka va>>10)
 
 	andi	k0, k0, ((NPTEPG/2) - 1) << 3	#0c: k0=page tab offset
 #xxx mips64 unsafe?
@@ -849,7 +849,7 @@ NLEAF(MipsTLBInvalidException)
 	nop
 
 	mfc0	k0, COP_0_BAD_VADDR
-	srl	k0, PGSHIFT - 2
+	srl	k0, PAGE_SHIFT - 2
 	andi	k0, 0xffc
 	PTR_ADDU	k1, k1, k0
 
@@ -933,7 +933,7 @@ tlb_insert_random:
 	sll	k1, k1, PAGE_SHIFT + 1
 
 	PTR_LA	k0, _C_LABEL(pcpu_space)
-	PTR_ADDU	k0, (NBPG * 2)
+	PTR_ADDU	k0, (PAGE_SIZE * 2)
 	PTR_ADDU	k0, k0, k1
 
 	/*

Modified: user/jmallett/octeon/sys/mips/mips/genassym.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/genassym.c	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/genassym.c	Sun Mar 28 02:48:39 2010	(r205787)
@@ -91,8 +91,8 @@ ASSYM(VM_KERNEL_ALLOC_OFFSET, VM_KERNEL_
 ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc));
 ASSYM(SIGFPE, SIGFPE);
 ASSYM(PAGE_SHIFT, PAGE_SHIFT);
-ASSYM(PGSHIFT, PGSHIFT);
-ASSYM(NBPG, NBPG);
+ASSYM(PAGE_SIZE, PAGE_SIZE);
+ASSYM(PAGE_MASK, PAGE_MASK);
 ASSYM(SEGSHIFT, SEGSHIFT);
 ASSYM(NPTEPG, NPTEPG);
 ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED);

Modified: user/jmallett/octeon/sys/mips/mips/locore.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/locore.S	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/locore.S	Sun Mar 28 02:48:39 2010	(r205787)
@@ -166,7 +166,7 @@ VECTOR(_locore, unknown)
 	 * Initialize stack and call machine startup.
 	 */
 	PTR_LA	sp, _C_LABEL(pcpu_space)
-	addiu	sp, (NBPG * 2) - CALLFRAME_SIZ
+	addiu	sp, (PAGE_SIZE * 2) - CALLFRAME_SIZ
 
 	sw	zero, CALLFRAME_SIZ - 4(sp)	# Zero out old ra for debugger
 	sw	zero, CALLFRAME_SIZ - 8(sp)	# Zero out old fp for debugger

Modified: user/jmallett/octeon/sys/mips/mips/mp_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mp_machdep.c	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/mp_machdep.c	Sun Mar 28 02:48:39 2010	(r205787)
@@ -246,7 +246,7 @@ smp_init_secondary(u_int32_t cpuid)
 	mips_dcache_wbinv_all();
 	mips_icache_sync_all();
 
-	MachSetPID(0);
+	Mips_SetPID(0);
 
 	pcpu_init(PCPU_ADDR(cpuid), cpuid, sizeof(struct pcpu));
 	dpcpu_init(dpcpu, cpuid);

Modified: user/jmallett/octeon/sys/mips/mips/mpboot.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/mpboot.S	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/mpboot.S	Sun Mar 28 02:48:39 2010	(r205787)
@@ -53,7 +53,7 @@ GLOBAL(mpentry)
 	 * Initialize stack and call machine startup
 	 */
 	PTR_LA	sp, _C_LABEL(pcpu_space)
-	addiu	sp, (NBPG * 2) - CALLFRAME_SIZ
+	addiu	sp, (PAGE_SIZE * 2) - CALLFRAME_SIZ
 	sll	t0, s0, PAGE_SHIFT + 1
 	addu	sp, sp, t0
 

Modified: user/jmallett/octeon/sys/mips/mips/pmap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/pmap.c	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/pmap.c	Sun Mar 28 02:48:39 2010	(r205787)
@@ -134,7 +134,7 @@ __FBSDID("$FreeBSD$");
 #define	NUSERPGTBLS		(pmap_segshift(VM_MAXUSER_ADDRESS))
 #define	MIPS_SEGSIZE		(1L << SEGSHIFT)
 #define	mips_segtrunc(va)	((va) & ~(MIPS_SEGSIZE-1))
-#define	pmap_TLB_invalidate_all() MIPS_TBIAP()
+#define	pmap_TLB_invalidate_all() mips_TBIAP(num_tlbentries)
 #define	pmap_va_asid(pmap, va)	((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT))
 #define	is_kernel_pmap(x)	((x) == kernel_pmap)
 
@@ -471,7 +471,7 @@ again:
 	kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
 	kernel_pmap->pm_asid[0].gen = 0;
 	pmap_max_asid = VMNUM_PIDS;
-	MachSetPID(0);
+	Mips_SetPID(0);
 }
 
 /*
@@ -587,8 +587,8 @@ pmap_invalidate_page_action(void *arg)
 		pmap->pm_asid[PCPU_GET(cpuid)].gen = 0;
 		return;
 	}
-	va = pmap_va_asid(pmap, (va & ~PGOFSET));
-	mips_TBIS(va);
+	va = pmap_va_asid(pmap, (va & ~PAGE_MASK));
+	Mips_TLBFlushAddr(va);
 }
 
 static void
@@ -596,9 +596,9 @@ pmap_TLB_invalidate_kernel(vm_offset_t v
 {
 	u_int32_t pid;
 
-	MachTLBGetPID(pid);
+	pid = Mips_TLBGetPID();
 	va = va | (pid << VMTLB_PID_SHIFT);
-	mips_TBIS(va);
+	Mips_TLBFlushAddr(va);
 }
 
 struct pmap_update_page_arg {
@@ -639,7 +639,7 @@ pmap_update_page_action(void *arg)
 		return;
 	}
 	va = pmap_va_asid(pmap, va);
-	MachTLBUpdate(va, pte);
+	Mips_TLBUpdate(va, pte);
 }
 
 static void
@@ -647,10 +647,10 @@ pmap_TLB_update_kernel(vm_offset_t va, p
 {
 	u_int32_t pid;
 
-	MachTLBGetPID(pid);
+	pid = Mips_TLBGetPID();
 	va = va | (pid << VMTLB_PID_SHIFT);
 
-	MachTLBUpdate(va, pte);
+	Mips_TLBUpdate(va, pte);
 }
 
 /*
@@ -743,7 +743,7 @@ pmap_kremove(vm_offset_t va)
 	/*
 	 * Write back all caches from the page being destroyed
 	 */
-	mips_dcache_wbinv_range_index(va, NBPG);
+	mips_dcache_wbinv_range_index(va, PAGE_SIZE);
 
 	pte = pmap_pte(kernel_pmap, va);
 	*pte = PTE_G;
@@ -866,19 +866,19 @@ pmap_init_fpage()
 	 * Make up start at an even page number so we can wire down the
 	 * fpage area in the tlb with a single tlb entry.
 	 */
-	if ((((vm_offset_t)kva) >> PGSHIFT) & 1) {
+	if ((((vm_offset_t)kva) >> PAGE_SHIFT) & 1) {
 		/*
 		 * 'kva' is not even-page aligned. Adjust it and free the
 		 * first page which is unused.
 		 */
-		kmem_free(kernel_map, (vm_offset_t)kva, NBPG);
-		kva = ((vm_offset_t)kva) + NBPG;
+		kmem_free(kernel_map, (vm_offset_t)kva, PAGE_SIZE);
+		kva = ((vm_offset_t)kva) + PAGE_SIZE;
 	} else {
 		/*
 		 * 'kva' is even page aligned. We don't need the last page,
 		 * free it.
 		 */
-		kmem_free(kernel_map, ((vm_offset_t)kva) + FSPACE, NBPG);
+		kmem_free(kernel_map, ((vm_offset_t)kva) + FSPACE, PAGE_SIZE);
 	}
 
 	for (i = 0; i < MAXCPU; i++) {
@@ -1655,7 +1655,7 @@ pmap_remove_page(struct pmap *pmap, vm_o
 	/*
 	 * Write back all caches from the page being destroyed
 	 */
-	mips_dcache_wbinv_range_index(va, NBPG);
+	mips_dcache_wbinv_range_index(va, PAGE_SIZE);
 
 	/*
 	 * get a local va for mappings for this pmap.
@@ -1742,7 +1742,7 @@ pmap_remove_all(vm_page_t m)
 		 * the page being destroyed
 	 	 */
 		if (m->md.pv_list_count == 1) 
-			mips_dcache_wbinv_range_index(pv->pv_va, NBPG);
+			mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
 
 		pv->pv_pmap->pm_stats.resident_count--;
 
@@ -2041,8 +2041,8 @@ validate:
 	 */
 	if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
 	    (prot & VM_PROT_EXECUTE)) {
-		mips_icache_sync_range(va, NBPG);
-		mips_dcache_wbinv_range(va, NBPG);
+		mips_icache_sync_range(va, PAGE_SIZE);
+		mips_dcache_wbinv_range(va, PAGE_SIZE);
 	}
 	vm_page_unlock_queues();
 	PMAP_UNLOCK(pmap);
@@ -2171,8 +2171,8 @@ pmap_enter_quick_locked(pmap_t pmap, vm_
 		 * unresolvable TLB miss may occur. */
 		if (pmap == &curproc->p_vmspace->vm_pmap) {
 			va &= ~PAGE_MASK;
-			mips_icache_sync_range(va, NBPG);
-			mips_dcache_wbinv_range(va, NBPG);
+			mips_icache_sync_range(va, PAGE_SIZE);
+			mips_dcache_wbinv_range(va, PAGE_SIZE);
 		}
 	}
 	return (mpte);
@@ -2577,7 +2577,7 @@ pmap_copy_page(vm_page_t src, vm_page_t 
 	{
 #if defined(__mips_n64)
 		pmap_flush_pvcache(src);
-		mips_dcache_wbinv_range_index(MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_dst), NBPG);
+		mips_dcache_wbinv_range_index(MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_dst), PAGE_SIZE);
 		va_src = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_src);
 		va_dst = MIPS_PHYS_TO_XKPHYS(MIPS_XKPHYS_CCA_CNC, phy_dst);
 		bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
@@ -2591,7 +2591,7 @@ pmap_copy_page(vm_page_t src, vm_page_t 
 			 */
 			pmap_flush_pvcache(src);
 			mips_dcache_wbinv_range_index(
-			    MIPS_PHYS_TO_KSEG0(phy_dst), NBPG);
+			    MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE);
 			va_src = MIPS_PHYS_TO_KSEG0(phy_src);
 			va_dst = MIPS_PHYS_TO_KSEG0(phy_dst);
 			bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
@@ -3112,7 +3112,7 @@ pmap_activate(struct thread *td)
 	pmap_asid_alloc(pmap);
 	if (td == curthread) {
 		PCPU_SET(segbase, pmap->pm_segtab);
-		MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid);
+		Mips_SetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid);
 	}
 
 	PCPU_SET(curpmap, pmap);
@@ -3285,7 +3285,7 @@ pmap_asid_alloc(pmap)
 	    pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
 	else {
 		if (PCPU_GET(next_asid) == pmap_max_asid) {
-			MIPS_TBIAP();
+			mips_TBIAP(num_tlbentries);
 			PCPU_SET(asid_generation,
 			    (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
 			if (PCPU_GET(asid_generation) == 0) {
@@ -3451,7 +3451,7 @@ pmap_flush_pvcache(vm_page_t m)
 	if (m != NULL) {
 		for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
 	    	    pv = TAILQ_NEXT(pv, pv_list)) {
-			mips_dcache_wbinv_range_index(pv->pv_va, NBPG);
+			mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
 		}
 	}
 }
@@ -3464,7 +3464,7 @@ pmap_save_tlb(void)
 	cpu = PCPU_GET(cpuid);
 
 	for (tlbno = 0; tlbno < num_tlbentries; ++tlbno)
-		MachTLBRead(tlbno, &tlbstash[cpu][tlbno]);
+		Mips_TLBRead(tlbno, &tlbstash[cpu][tlbno]);
 }
 
 #ifdef DDB

Modified: user/jmallett/octeon/sys/mips/mips/support.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/support.S	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/support.S	Sun Mar 28 02:48:39 2010	(r205787)
@@ -185,7 +185,7 @@ END(fillw)
  * mem_zero_page(addr);
  */
 LEAF(mem_zero_page)
-	li	v0, NBPG
+	li	v0, PAGE_SIZE
 1:
 	subu	v0, 8
 	sd	zero, 0(a0)

Modified: user/jmallett/octeon/sys/mips/mips/tlb.S
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/tlb.S	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/tlb.S	Sun Mar 28 02:48:39 2010	(r205787)
@@ -225,7 +225,7 @@ LEAF(Mips_TLBFlush)
 	# MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
 	# One bogus value for every TLB entry might cause MCHECK exception
 	#
-	sll	t3, t1, PGSHIFT + 1
+	sll	t3, t1, PAGE_SHIFT + 1
 	li	v0, MIPS_KSEG0_START		# invalid address
 	addu	v0, t3
 /*
@@ -284,7 +284,7 @@ LEAF(Mips_TLBFlushAddr)
 	# address calculated by following expression:
 	# MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
 	# One bogus value for every TLB entry might cause MCHECK exception
-	sll	v0, PGSHIFT + 1
+	sll	v0, PAGE_SHIFT + 1
 	addu	t1, v0
 	MTC0	t1, COP_0_TLB_HI		# Mark entry high as invalid
 
@@ -467,7 +467,7 @@ LEAF(mips_TBIAP)
 	# MIPS_KSEG0_START + 2 * i * PAGE_SIZE;
 	# One bogus value for every TLB entry might cause MCHECK exception
 	#
-	sll	t3, t1, PGSHIFT + 1
+	sll	t3, t1, PAGE_SHIFT + 1
 	li	v0, MIPS_KSEG0_START		# invalid address
 	addu	v0, t3
 
@@ -492,7 +492,7 @@ LEAF(mips_TBIAP)
 	tlbwi					# invalidate the TLB entry
 2:
 	addu	t1, t1, 1
-	addu	v0, 1 << (PGSHIFT + 1)
+	addu	v0, 1 << (PAGE_SHIFT + 1)
 	bne	t1, t2, 1b
 	nop
 

Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/trap.c	Sun Mar 28 02:48:39 2010	(r205787)
@@ -330,7 +330,7 @@ trap(struct trapframe *trapframe)
 #ifdef SMP
 		printf("cpuid = %d\n", PCPU_GET(cpuid));
 #endif
-		MachTLBGetPID(pid);
+		pid = Mips_TLBGetPID();
 		printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
 		    (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
 		    (intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
@@ -379,12 +379,12 @@ trap(struct trapframe *trapframe)
 			if (!(pte = pmap_segmap(kernel_pmap,
 			    trapframe->badvaddr)))
 				panic("trap: ktlbmod: invalid segmap");
-			pte += (trapframe->badvaddr >> PGSHIFT) & (NPTEPG - 1);
+			pte += (trapframe->badvaddr >> PAGE_SHIFT) & (NPTEPG - 1);
 			entry = *pte;
 #ifdef SMP
 			/* It is possible that some other CPU changed m-bit */
 			if (!mips_pg_v(entry) || (entry & mips_pg_m_bit())) {
-				trapframe->badvaddr &= ~PGOFSET;
+				trapframe->badvaddr &= ~PAGE_MASK;
 				pmap_update_page(kernel_pmap,
 				    trapframe->badvaddr, entry);
 				PMAP_UNLOCK(kernel_pmap);
@@ -402,7 +402,7 @@ trap(struct trapframe *trapframe)
 			}
 			entry |= mips_pg_m_bit();
 			*pte = entry;
-			trapframe->badvaddr &= ~PGOFSET;
+			trapframe->badvaddr &= ~PAGE_MASK;
 			pmap_update_page(kernel_pmap, trapframe->badvaddr, entry);
 			pa = mips_tlbpfn_to_paddr(entry);
 			if (!page_is_managed(pa))
@@ -422,12 +422,12 @@ trap(struct trapframe *trapframe)
 			PMAP_LOCK(pmap);
 			if (!(pte = pmap_segmap(pmap, trapframe->badvaddr)))
 				panic("trap: utlbmod: invalid segmap");
-			pte += (trapframe->badvaddr >> PGSHIFT) & (NPTEPG - 1);
+			pte += (trapframe->badvaddr >> PAGE_SHIFT) & (NPTEPG - 1);
 			entry = *pte;
 #ifdef SMP
 			/* It is possible that some other CPU changed m-bit */
 			if (!mips_pg_v(entry) || (entry & mips_pg_m_bit())) {
-				trapframe->badvaddr = (trapframe->badvaddr & ~PGOFSET);
+				trapframe->badvaddr = (trapframe->badvaddr & ~PAGE_MASK);
 				pmap_update_page(pmap, trapframe->badvaddr, entry);
 				PMAP_UNLOCK(pmap);
 				goto out;
@@ -446,7 +446,7 @@ trap(struct trapframe *trapframe)
 			}
 			entry |= mips_pg_m_bit();
 			*pte = entry;
-			trapframe->badvaddr = (trapframe->badvaddr & ~PGOFSET);
+			trapframe->badvaddr = (trapframe->badvaddr & ~PAGE_MASK);
 			pmap_update_page(pmap, trapframe->badvaddr, entry);
 			trapframe->badvaddr |= (pmap->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT);
 			pa = mips_tlbpfn_to_paddr(entry);
@@ -932,7 +932,7 @@ dofault:
 #endif
 
 	case T_FPE + T_USER:
-		MachFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
+		MipsFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
 		goto out;
 
 	case T_OVFLOW + T_USER:

Modified: user/jmallett/octeon/sys/mips/mips/vm_machdep.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/vm_machdep.c	Sun Mar 28 02:44:33 2010	(r205786)
+++ user/jmallett/octeon/sys/mips/mips/vm_machdep.c	Sun Mar 28 02:48:39 2010	(r205787)
@@ -234,7 +234,7 @@ cpu_thread_swapin(struct thread *td)
 	 */
 	if (!(pte = pmap_segmap(kernel_pmap, td->td_md.md_realstack)))
 		panic("cpu_thread_swapin: invalid segmap");
-	pte += ((vm_offset_t)td->td_md.md_realstack >> PGSHIFT) & (NPTEPG - 1);
+	pte += ((vm_offset_t)td->td_md.md_realstack >> PAGE_SHIFT) & (NPTEPG - 1);
 
 	for (i = 0; i < KSTACK_PAGES - 1; i++) {
 		td->td_md.md_upte[i] = *pte & ~(PTE_RO|PTE_WIRED);
@@ -270,7 +270,7 @@ cpu_thread_alloc(struct thread *td)
 
 	if (!(pte = pmap_segmap(kernel_pmap, td->td_md.md_realstack)))
 		panic("cpu_thread_alloc: invalid segmap");
-	pte += ((vm_offset_t)td->td_md.md_realstack >> PGSHIFT) & (NPTEPG - 1);
+	pte += ((vm_offset_t)td->td_md.md_realstack >> PAGE_SHIFT) & (NPTEPG - 1);
 
 	for (i = 0; i < KSTACK_PAGES - 1; i++) {
 		td->td_md.md_upte[i] = *pte & ~(PTE_RO|PTE_WIRED);



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