Date: Mon, 6 Apr 2015 12:49:39 +0000 From: Alexey Dokuchaev <danfe@FreeBSD.org> To: John Baldwin <jhb@FreeBSD.org> Cc: svn-src-stable@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org, svn-src-stable-9@freebsd.org Subject: Re: svn commit: r280973 - in stable: 10/sys/amd64/amd64 10/sys/dev/acpica 10/sys/i386/i386 10/sys/kern 10/sys/sys 10/sys/x86/x86 9/sys/amd64/amd64 9/sys/dev/acpica 9/sys/i386/i386 9/sys/kern 9/sys/sys ... Message-ID: <20150406124939.GA48665@FreeBSD.org> In-Reply-To: <201504020102.t3212lTO021499@svn.freebsd.org> References: <201504020102.t3212lTO021499@svn.freebsd.org>
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On Thu, Apr 02, 2015 at 01:02:47AM +0000, John Baldwin wrote: > New Revision: 280973 > URL: https://svnweb.freebsd.org/changeset/base/280973 > > Log: > MFC 276724: > On some Intel CPUs with a P-state but not C-state invariant TSC the TSC > may also halt in C2 and not just C3 (it seems that in some cases the BIOS > advertises its C3 state as a C2 state in _CST). Just play it safe and > disable both C2 and C3 states if a user forces the use of the TSC as the > timecounter on such CPUs. Does it apply to stable/8 as well? Any preliminary testing I might have to conduct first? ./danfe
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