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Date:      Sun, 15 Dec 1996 12:03:59 -0800
From:      Amancio Hasty <>
Subject:   Re: PCI 2.1 Byte Enables? 
Message-ID:  <>
In-Reply-To: Your message of "Sun, 15 Dec 1996 13:45:09 GMT." <"1c28-961215134504-FCA1*/S=FreeBSD/O=NET-TEL Computer Systems Ltd/PRMD=NET-TEL/ADMD=Gold 400/C=GB/"@MHS> 

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>From The Desk Of :
> > I am writing a device driver for a PCI video capture board,
> > Brooktree Bt848,as part of  a dma risc instruction it requires :
> > byte count and 4 bits for PCI byte enables.
> > 
> > Can anyone guess what the PCI byte enables are for?
> PCI transfers operate on 32-bit words, and are always addressed on 4-byte
> boundaries.  With each word transferred, there are 4 byte-enable signals
> to indicate which of the 4 bytes are in use.
> So, to do a DMA transfer of an abritrary byte-aligned block of memory,
> you would do one cycle with byte enables adjusted to pick up the first
> 1,2, or 3 bytes to bring you to a word boundary, then a number of
> cycles with all 4 byte enables active, then a last cycle with byte
> enables set to write the write number of bytes.
> On the bus, the byte enables are 4 bits, one for each byte of the
> 32-bit word, and are "1" for disable, "0" for enable.  You are not
> required to set them contiguously - you could transfer alternate
> bytes by setting the enables appropriately if you felt like it.
> However, you would expect two sets of byte enable settings for an
> arbitrary DMA transfer (starting/ending), so your chip must be doing
> somthing more sophisticated - maybe you give it the starting
> byte enables and it computes the ending ones from the byte count?


I am going out today and get a PCI book not just for the PCI Byte enables
issue but to find out more about the PCI bus.

At any rate, this is what the risc instruction looks like:

WRITE opcode 0001  --- Write Packed mode Pixels to memory from the FIFO
                      beginning at the specified target address.
 11:0   Byte Count
 15:12  Byte Enables
 23:16  Reset/Set RISC_STATUS
 24     IRQ
 25     Reserved
 26     EOL       - End of line
 27     SOL       - Start of Line
 31:28  Opcode

 31:0   Target Address (buffer to dump video to)


 WRITEC opcode 0101  --- Write Packed mode pixels to memory from the FIFO
	                continuing from the current target address.
		        (packed mode is rgb32, rgb24, or rgb16)

 11:0   Byte Count
 15:12  Byte Enables
 23:16  Reset/Set RISC_STATUS
 24     IRQ
 25     Reserved
 26     EOL       - End of Line
 27     SOL       - Start of Line bit not used in this instruction
 31:28  Opcode


A "dma risc program" can have one or more "WRITE" or WRITEC instructions.
In the case of a "WRITEC" instruction, the DMA transfer must be first
initiated by a "WRITE" instruction with the "SOL" bit set

According to the databook a "WRITE" can have both EOL and SOL set which
implies that the Bt848 is capable of starting and ending a DMA transfer.
Since, I am transferring rgb32 -- 4bytes per pixel and my buffer is
dword aligned my guess is that PCI Byte Enables should be 0.

Tnks also to all who responded...


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