Date: Sun, 15 Dec 2013 15:37:07 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r259415 - projects/specific_leg/sys/arm/include Message-ID: <201312151537.rBFFb70t065140@svn.freebsd.org>
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Author: andrew Date: Sun Dec 15 15:37:07 2013 New Revision: 259415 URL: http://svnweb.freebsd.org/changeset/base/259415 Log: Reorder pmap.h to check for a v6+ MMU first. We are unable to have both v4/5 and v6/7 in the kernel. Modified: projects/specific_leg/sys/arm/include/cpuconf.h projects/specific_leg/sys/arm/include/pmap.h Modified: projects/specific_leg/sys/arm/include/cpuconf.h ============================================================================== --- projects/specific_leg/sys/arm/include/cpuconf.h Sun Dec 15 13:15:38 2013 (r259414) +++ projects/specific_leg/sys/arm/include/cpuconf.h Sun Dec 15 15:37:07 2013 (r259415) @@ -183,6 +183,11 @@ #error ARM_NMMUS is 0 #endif +#if (ARM_MMU_V6 + ARM_MMU_V7) > 0 && ARM_NMMUS != (ARM_MMU_V6 + ARM_MMU_V7) +#error Unable to mix pre-v6 MMUs with post-v6 MMUs +#endif + + /* * Step 4: Define features that may be present on a subset of CPUs * Modified: projects/specific_leg/sys/arm/include/pmap.h ============================================================================== --- projects/specific_leg/sys/arm/include/pmap.h Sun Dec 15 13:15:38 2013 (r259414) +++ projects/specific_leg/sys/arm/include/pmap.h Sun Dec 15 15:37:07 2013 (r259415) @@ -341,47 +341,7 @@ extern int pmap_needs_pte_sync; #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) #endif -#if ARM_NMMUS > 1 -/* More than one MMU class configured; use variables. */ -#define L2_S_PROT_U pte_l2_s_prot_u -#define L2_S_PROT_W pte_l2_s_prot_w -#define L2_S_PROT_MASK pte_l2_s_prot_mask - -#define L1_S_CACHE_MASK pte_l1_s_cache_mask -#define L2_L_CACHE_MASK pte_l2_l_cache_mask -#define L2_S_CACHE_MASK pte_l2_s_cache_mask - -#define L1_S_PROTO pte_l1_s_proto -#define L1_C_PROTO pte_l1_c_proto -#define L2_S_PROTO pte_l2_s_proto - -#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 -#define L2_S_PROT_U L2_S_PROT_U_generic -#define L2_S_PROT_W L2_S_PROT_W_generic -#define L2_S_PROT_MASK L2_S_PROT_MASK_generic - -#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic -#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic -#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic - -#define L1_S_PROTO L1_S_PROTO_generic -#define L1_C_PROTO L1_C_PROTO_generic -#define L2_S_PROTO L2_S_PROTO_generic - -#elif ARM_MMU_XSCALE == 1 -#define L2_S_PROT_U L2_S_PROT_U_xscale -#define L2_S_PROT_W L2_S_PROT_W_xscale -#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale - -#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale -#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale -#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale - -#define L1_S_PROTO L1_S_PROTO_xscale -#define L1_C_PROTO L1_C_PROTO_xscale -#define L2_S_PROTO L2_S_PROTO_xscale - -#elif (ARM_MMU_V6 + ARM_MMU_V7) != 0 +#if (ARM_MMU_V6 + ARM_MMU_V7) != 0 /* * AP[2:1] access permissions model: * @@ -486,7 +446,48 @@ extern int pmap_needs_pte_sync; #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) #endif /* SMP */ -#endif /* ARM_NMMUS > 1 */ + +#elif ARM_NMMUS > 1 /* This will only work for pre-v6 MMUs */ +/* More than one MMU class configured; use variables. */ +#define L2_S_PROT_U pte_l2_s_prot_u +#define L2_S_PROT_W pte_l2_s_prot_w +#define L2_S_PROT_MASK pte_l2_s_prot_mask + +#define L1_S_CACHE_MASK pte_l1_s_cache_mask +#define L2_L_CACHE_MASK pte_l2_l_cache_mask +#define L2_S_CACHE_MASK pte_l2_s_cache_mask + +#define L1_S_PROTO pte_l1_s_proto +#define L1_C_PROTO pte_l1_c_proto +#define L2_S_PROTO pte_l2_s_proto + +#elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 +#define L2_S_PROT_U L2_S_PROT_U_generic +#define L2_S_PROT_W L2_S_PROT_W_generic +#define L2_S_PROT_MASK L2_S_PROT_MASK_generic + +#define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic +#define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic +#define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic + +#define L1_S_PROTO L1_S_PROTO_generic +#define L1_C_PROTO L1_C_PROTO_generic +#define L2_S_PROTO L2_S_PROTO_generic + +#elif ARM_MMU_XSCALE == 1 +#define L2_S_PROT_U L2_S_PROT_U_xscale +#define L2_S_PROT_W L2_S_PROT_W_xscale +#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale + +#define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale +#define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale +#define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale + +#define L1_S_PROTO L1_S_PROTO_xscale +#define L1_C_PROTO L1_C_PROTO_xscale +#define L2_S_PROTO L2_S_PROTO_xscale + +#endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */ #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) #define PMAP_NEEDS_PTE_SYNC 1
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