Date: Thu, 27 Sep 2007 23:46:33 +0200 From: Marius Nuennerich <marius.nuennerich@gmx.de> To: freebsd-arm@freebsd.org Subject: Re: Comment bug in locore.S? Message-ID: <20070927234633.50c1789d@sol.hackerzberg.local> In-Reply-To: <20070927221027.GA16476@ci0.org> References: <20070927171822.0bdec7d9@sol.hackerzberg.local> <20070927170339.GA11021@ci0.org> <20070927224133.5fc9b24f@sol.hackerzberg.local> <20070927214141.GB15654@ci0.org> <20070927231331.5d22bf4a@sol.hackerzberg.local> <20070927221027.GA16476@ci0.org>
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--MP_yNwvVYRlL_INXBJL=K=zM_g Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Disposition: inline On Fri, 28 Sep 2007 00:10:27 +0200 Olivier Houchard <mlfbsd@ci0.org> wrote: > On Thu, Sep 27, 2007 at 11:13:31PM +0200, Marius Nuennerich wrote: > > On Thu, 27 Sep 2007 23:41:41 +0200 > > Olivier Houchard <mlfbsd@ci0.org> wrote: > > > > > On Thu, Sep 27, 2007 at 10:41:33PM +0200, Marius Nuennerich wrote: > > > > On Thu, 27 Sep 2007 19:03:39 +0200 > > > > Olivier Houchard <mlfbsd@ci0.org> wrote: > > > > > > > > > On Thu, Sep 27, 2007 at 05:18:22PM +0200, Marius Nuennerich wrote: > > > > > > Hi all, > > > > > > > > > > > > > > > > Hi Marius, > > > > > > > > > > > I'm still trying to boot FreeBSD on the neo1973. So far I managed to > > > > > > put bytes over the serial console so I can see where I am. At the > > > > > > moment the (virtual) machine crashes in locore.S (1.16) line 170: > > > > > > ldr pc, .Lvirt_done > > > > > > > > > > > > qemu: fatal: Trying to execute code outside RAM or ROM at 0xc0008??? > > > > > > > > > > > > Which I don't understand because the section should be mapped by the > > > > > > MMU to 0x30008??? at that time. > > > > > > > > > > > > In line 137 the sequence in the comment is described as > > > > > > /* # of sections, PA|attr, VA */ > > > > > > but in line 185 the order is > > > > > > n_sec, VA, PA|attr > > > > > > > > > > > > Is the comment wrong? > > > > > > > > > > > > > > > > No the comment is right, 0xc0000000 should be mapped. > > > > > Did you define STARTUP_PAGETABLE_ADDR ? It's not marked as such, but it is > > > > > mandatory now. > > > > > > > > Yes, in the kernel config there are these lines: > > > > makeoptions KERNPHYSADDR=0x30008000 > > > > makeoptions KERNVIRTADDR=0xc0000000 > > > > options KERNPHYSADDR=0x30008000 > > > > options KERNVIRTADDR=0xc0000000 > > > > options PHYSADDR=0x30000000 > > > > options STARTUP_PAGETABLE_ADDR=0x30800000 > > > > > > > > It's from Andrew Turners config file which he posted on > > > > http://wiki.openmoko.org/wiki/FreeBSD > > > > in the tarball. > > > > > > > > > > Hmmm, I really see no reason why the PA <=> PA mapping would work, but not > > > the VA <=> PA one. > > > I'll try to setup qemu. Can it provide useful informations about its > > > internal state, ie CPU registers, TLB, etc ? > > > > Yes, it looks like this: > > qemu: fatal: Trying to execute code outside RAM or ROM at 0xc0008030 > > > > R00=30800000 R01=c01afdb8 R02=c0000070 R03=00000000 > > R04=3000824c R05=3000808c R06=00000002 R07=30008050 > > R08=33f17fdc R09=00000000 R10=00000041 R11=50000020 > > R12=33f14934 R13=c019b140 R14=33f8b9e8 R15=c0008030 > > PSR=60000153 -ZC- A svc32 > > There's something I seriously miss. At this point, r2 should be 0 : > ldmia r1, {r1, r2, sp} /* Set initial stack and */ > sub r2, r2, r1 /* get zero init data */ > mov r3, #0 > .L1: > str r3, [r1], #0x0004 /* get zero init data */ > subs r2, r2, #4 > bgt .L1 > ldr pc, .Lvirt_done > > And not 0xc0000070 > What are the values of _edata and _end ? > If you've been able to do all those stores, the mapping should work anyway, > I'm really confused. I'm sorry, I just realized that it doesn't crash right there. My debug ouput on serial line is ACDFFFGabcdeHIfA which indicates that it does jump but to an address before line 110. I attach my modified locore.S hopefully it won't get scrubbed. --MP_yNwvVYRlL_INXBJL=K=zM_g Content-Type: text/plain; name=locore.S.txt Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=locore.S.txt /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */ /*- * Copyright (C) 1994-1997 Mark Brinicombe * Copyright (C) 1994 Brini * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of Brini may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include "assym.s" #include <sys/syscall.h> #include <machine/asm.h> #include <machine/armreg.h> #include <machine/pte.h> __FBSDID("$FreeBSD: src/sys/arm/arm/locore.S,v 1.16 2007/02/26 02:03:48 cognet Exp $"); /* What size should this really be ? It is only used by initarm() */ #define INIT_ARM_STACK_SIZE 2048 /* * This is for kvm_mkdb, and should be the address of the beginning * of the kernel text segment (not necessarily the same as kernbase). */ #define CPWAIT_BRANCH \ sub pc, pc, #4 #define CPWAIT(tmp) \ mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ mov tmp, tmp /* wait for it to complete */ ;\ CPWAIT_BRANCH /* branch to next insn */ #define PRINT(char) \ mov r11, #0x50000000 ;\ add r11, r11, #32 ;\ mov r10, ##char ;\ strb r10, [r11] .text .align 0 .globl kernbase .set kernbase,KERNBASE .globl physaddr .set physaddr,PHYSADDR ENTRY_NP(btext) ASENTRY_NP(_start) #if defined (FLASHADDR) && defined(LOADERRAMADDR) /* Check if we're running from flash. */ ldr r7, =FLASHADDR /* * If we're running with MMU disabled, test against the * physical address instead. */ mrc p15, 0, r2, c1, c0, 0 ands r2, r2, #CPU_CONTROL_MMU_ENABLE ldreq r8, =PHYSADDR ldrne r8, =LOADERRAMADDR cmp r7, r8 bls flash_lower cmp r7, pc bhi from_ram b do_copy flash_lower: cmp r8, pc bls from_ram do_copy: ldr r9, =KERNBASE adr r1, _start ldr r0, Lreal_start ldr r2, Lend sub r2, r2, r0 sub r0, r0, r9 add r0, r0, r8 mov r4, r0 bl memcpy ldr r0, Lram_offset add pc, r4, r0 Lram_offset: .word from_ram-_C_LABEL(_start) from_ram: nop #endif adr r7, Lunmapped bic r7, r7, #0xff000000 orr r7, r7, #PHYSADDR PRINT(#'A') disable_mmu: /* Disable MMU for a while */ mrc p15, 0, r2, c1, c0, 0 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\ CPU_CONTROL_WBUF_ENABLE) bic r2, r2, #(CPU_CONTROL_IC_ENABLE) bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE) mcr p15, 0, r2, c1, c0, 0 nop nop nop mov pc, r7 PRINT(#'B') Lunmapped: PRINT(#'C') #ifdef STARTUP_PAGETABLE_ADDR PRINT(#'D') /* build page table from scratch */ ldr r0, Lstartup_pagetable adr r4, mmu_init_table b 3f PRINT(#'E') 2: str r3, [r0, r2] add r2, r2, #4 add r3, r3, #(L1_S_SIZE) adds r1, r1, #-1 bhi 2b PRINT(#'F') 3: ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ cmp r1, #0 adrne r5, 2b bicne r5, r5, #0xff000000 orrne r5, r5, #PHYSADDR movne pc, r5 PRINT(#'G') mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ PRINT(#'a') mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ PRINT(#'b') /* Set the Domain Access register. Very important! */ mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) mcr p15, 0, r0, c3, c0, 0 PRINT(#'c') /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 PRINT(#'d') orr r0, r0, #CPU_CONTROL_MMU_ENABLE mcr p15, 0, r0, c1, c0, 0 PRINT(#'e') nop nop nop CPWAIT(r0) PRINT(#'H') #endif mmu_done: nop adr r1, .Lstart ldmia r1, {r1, r2, sp} /* Set initial stack and */ sub r2, r2, r1 /* get zero init data */ mov r3, #0 PRINT(#'I') .L1: str r3, [r1], #0x0004 /* get zero init data */ subs r2, r2, #4 bgt .L1 PRINT(#'f') ldr pc, .Lvirt_done PRINT(#'J') virt_done: PRINT(#'K') mov fp, #0 /* trace back starts here */ bl _C_LABEL(initarm) /* Off we go */ PRINT(#'L') /* init arm will return the new stack pointer. */ mov sp, r0 bl _C_LABEL(mi_startup) /* call mi_startup()! */ PRINT(#'M') adr r0, .Lmainreturned b _C_LABEL(panic) /* NOTEACHED */ #ifdef STARTUP_PAGETABLE_ADDR #define MMU_INIT(va,pa,n_sec,attr) \ .word n_sec ; \ .word 4*((va)>>L1_S_SHIFT) ; \ .word (pa)|(attr) ; Lvirtaddr: .word KERNVIRTADDR Lphysaddr: .word KERNPHYSADDR Lreal_start: .word _start Lend: .word _edata Lstartup_pagetable: .word STARTUP_PAGETABLE_ADDR mmu_init_table: /* fill all table VA==PA */ /* map SDRAM VA==PA, WT cacheable */ MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) /* map VA 0xc0000000..0xc3ffffff to PA */ MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) /* map UART */ MMU_INIT(0x50000000, 0x50000000, 1, L1_TYPE_S|L1_S_AP(AP_KRW)) .word 0 /* end of table */ #endif .Lstart: .word _edata .word _end .word svcstk + INIT_ARM_STACK_SIZE #if defined(FLASHADDR) && defined(LOADERRAMADDR) .L_arm_memcpy: .word _C_LABEL(_arm_memcpy) #endif .Lvirt_done: .word virt_done .Lmainreturned: .asciz "main() returned" .align 0 .bss svcstk: .space INIT_ARM_STACK_SIZE .text .align 0 #ifndef OFW /* OFW based systems will used OF_boot() */ .Lcpufuncs: .word _C_LABEL(cpufuncs) ENTRY_NP(cpu_halt) mrs r2, cpsr bic r2, r2, #(PSR_MODE) orr r2, r2, #(PSR_SVC32_MODE) orr r2, r2, #(I32_bit | F32_bit) msr cpsr_all, r2 ldr r4, .Lcpu_reset_address ldr r4, [r4] ldr r0, .Lcpufuncs mov lr, pc ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] /* * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's * necessary. */ ldr r1, .Lcpu_reset_needs_v4_MMU_disable ldr r1, [r1] cmp r1, #0 mov r2, #0 /* * MMU & IDC off, 32 bit program & data space * Hurl ourselves into the ROM */ mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE) mcr 15, 0, r0, c1, c0, 0 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */ mov pc, r4 /* * _cpu_reset_address contains the address to branch to, to complete * the cpu reset after turning the MMU off * This variable is provided by the hardware specific code */ .Lcpu_reset_address: .word _C_LABEL(cpu_reset_address) /* * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the * v4 MMU disable instruction needs executing... it is an illegal instruction * on f.e. ARM6/7 that locks up the computer in an endless illegal * instruction / data-abort / reset loop. */ .Lcpu_reset_needs_v4_MMU_disable: .word _C_LABEL(cpu_reset_needs_v4_MMU_disable) #endif /* OFW */ #ifdef IPKDB /* * Execute(inst, psr, args, sp) * * Execute INSTruction with PSR and ARGS[0] - ARGS[3] making * available stack at SP for next undefined instruction trap. * * Move the instruction onto the stack and jump to it. */ ENTRY_NP(Execute) mov ip, sp stmfd sp!, {r2, r4-r7, fp, ip, lr, pc} sub fp, ip, #4 mov ip, r3 ldr r7, .Lreturn stmfd sp!, {r0, r7} adr r7, #.LExec mov r5, r1 mrs r4, cpsr ldmia r2, {r0-r3} mov r6, sp mov sp, ip msr cpsr_all, r5 mov pc, r6 .LExec: mrs r5, cpsr /* XXX Cannot switch thus easily back from user mode */ msr cpsr_all, r4 add sp, r6, #8 ldmfd sp!, {r6} stmia r6, {r0-r3} mov r0, r5 ldmdb fp, {r4-r7, fp, sp, pc} .Lreturn: mov pc, r7 #endif /* * setjump + longjmp */ ENTRY(setjmp) stmia r0, {r4-r14} mov r0, #0x00000000 RET ENTRY(longjmp) ldmia r0, {r4-r14} mov r0, #0x00000001 RET .data .global _C_LABEL(esym) _C_LABEL(esym): .word _C_LABEL(end) ENTRY_NP(abort) b _C_LABEL(abort) ENTRY_NP(sigcode) mov r0, sp swi SYS_sigreturn /* Well if that failed we better exit quick ! */ swi SYS_exit b . - 8 .align 0 .global _C_LABEL(esigcode) _C_LABEL(esigcode): .data .global szsigcode szsigcode: .long esigcode-sigcode /* End of locore.S */ --MP_yNwvVYRlL_INXBJL=K=zM_g--
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