Date: Sat, 17 Jul 2010 11:54:32 -0600 (MDT) From: "M. Warner Losh" <imp@bsdimp.com> To: mav@FreeBSD.ORG Cc: neel@FreeBSD.ORG, freebsd-mips@FreeBSD.ORG Subject: Re: [RFC] Event timers on MIPS Message-ID: <20100717.115432.680326283860859045.imp@bsdimp.com> In-Reply-To: <4C41E94D.5030206@FreeBSD.org> References: <4C41A248.8090605@FreeBSD.org> <20100717.112233.994790107173916507.imp@bsdimp.com> <4C41E94D.5030206@FreeBSD.org>
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In message: <4C41E94D.5030206@FreeBSD.org> Alexander Motin <mav@FreeBSD.ORG> writes: : M. Warner Losh wrote: : > In message: <4C41A248.8090605@FreeBSD.org> : > Alexander Motin <mav@FreeBSD.org> writes: : > : I've made a patch, updating MIPS timer code (except RMI) to utilize new : > : MI event timer infrastructure. I've successfully built QEMU and XLR : > : kernels with the patch. Unluckily I can't test how it works, unless : > : somebody teach me how to cook QEMU to run it. I also haven't ported RMI : > : timers drivers, as I am not sure how that hardware is intended to work. : > : : > : Patch for HEAD can be found here: : > : http://people.freebsd.org/~mav/timers_mips.patch : > : > I'll have to take a look at things. On MIPS, the COMPARE register is : > per core, so you don't need to send an IPI if you are using that : > hardware. IPIs are a little expensive, IIRC, since they tend to have : > bad cache effects and put extra pressure on the TLBs. : > : > It wasn't clear from these patches if you are using one core to do the : > signalling for all the others or not. If so, that represents a bit of : > a regression. I'm also not sure about not having a per-cpu timer's : > effect on performance on a 16 or 32 core MIPS box... : : I am registering event timer as per-CPU: : + sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | : + ET_FLAGS_PERCPU; : : Clock IPI's added only for completeness, in case there will be supported : any other non-per-CPU timers, like mentioned PIC clock on XLR. That sounds good.... Warner
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