Date: Sun, 22 May 2005 01:19:40 -0700 From: Marcel Moolenaar <marcel@xcllnt.net> To: Colin Percival <cperciva@freebsd.org> Cc: freebsd-arch@freebsd.org Subject: Re: Scheduler fixes for hyperthreading Message-ID: <401480a79de1cc474eec20c1943da574@xcllnt.net> In-Reply-To: <42900C01.10904@freebsd.org> References: <428FC00B.3080909@freebsd.org> <aef05e1ae6104223181ad3cf03e11390@xcllnt.net> <428FD710.4060200@freebsd.org> <9e8314b53980a379445cc8c07086901d@xcllnt.net> <428FE788.8020408@freebsd.org> <6451b639f2e0ddacb18f62c571dfeedb@xcllnt.net> <42900C01.10904@freebsd.org>
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On May 21, 2005, at 9:35 PM, Colin Percival wrote: > Marcel Moolenaar wrote: >> There are a lot of variables that need to be taken into account and >> those variables do not necessarily map perfectly from a P4 to an I2. >> Sharing of the L1 cache is not a sufficient condition to create a >> side-channel for timing attacks. A reliable time source with enough >> precision is also necessary (as you and Stephan have pointed out). >> The precision of the time source depends on latencies of the various >> cache levels and the micro-architectural behavior of the processor. > > Point taken. I maintain, however, that it is much better to make > "information can leak between these processors" a machine-independent > concept which is handled appropriately by the scheduler (with the > necessary machine-dependent code to specify *which* sets of processors, > if any, have such leakage). Yes, I agree. I forgot to explicitly acknowledge that point in my previous emails. Sorry about that... -- Marcel Moolenaar USPA: A-39004 marcel@xcllnt.net
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