Date: Tue, 20 Oct 2009 04:36:08 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r198264 - projects/mips/sys/mips/mips Message-ID: <200910200436.n9K4a8CA053249@svn.freebsd.org>
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Author: neel Date: Tue Oct 20 04:36:08 2009 New Revision: 198264 URL: http://svn.freebsd.org/changeset/base/198264 Log: Fix a bug where we would think that the L1 instruction and data cache are present even though the line size field in the CP0 Config1 register is 0. Approved by: imp (mentor) Modified: projects/mips/sys/mips/mips/cpu.c Modified: projects/mips/sys/mips/mips/cpu.c ============================================================================== --- projects/mips/sys/mips/mips/cpu.c Tue Oct 20 04:31:20 2009 (r198263) +++ projects/mips/sys/mips/mips/cpu.c Tue Oct 20 04:36:08 2009 (r198264) @@ -94,9 +94,9 @@ mips_get_identity(struct mips_cpuinfo *c ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; /* L1 instruction cache. */ - tmp = 1 << (((cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT) + 1); + tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; if (tmp != 0) { - cpuinfo->l1.ic_linesize = tmp; + cpuinfo->l1.ic_linesize = 1 << (tmp + 1); cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); @@ -105,9 +105,9 @@ mips_get_identity(struct mips_cpuinfo *c } /* L1 data cache. */ - tmp = 1 << (((cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT) + 1); + tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; if (tmp != 0) { - cpuinfo->l1.dc_linesize = tmp; + cpuinfo->l1.dc_linesize = 1 << (tmp + 1); cpuinfo->l1.dc_nways = (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; cpuinfo->l1.dc_nsets =
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