Date: Thu, 4 Dec 2008 16:45:53 -0800 From: "Ravi Murty" <ravi.murty@gmail.com> To: freebsd-hackers@freebsd.org Subject: local APIC 2 interrupt fifo limit Message-ID: <95b10a340812041645t770b1d8sc7802773ab6beff2@mail.gmail.com>
next in thread | raw e-mail | index | archive | help
Hello, There is this comment in apicvar.h in the amd64 tree that talks about why the kernel uses smp_ipi_mtx and how it prevents more than 2 outstanding IPIs per interrupt vector. It appears that modern CPUs collapse the IRR bit if there is an interrupt when both the IRR and ISR bits are set. I was wondering why we need smp_ipi_mtx besides the fact that the kernel uses global variables for things like invalidate page ranges. Thanks, Ravi
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?95b10a340812041645t770b1d8sc7802773ab6beff2>