Date: Mon, 21 Jan 2002 12:55:23 +1100 From: Peter Jeremy <peter.jeremy@alcatel.com.au> To: Garrett Wollman <wollman@khavrinen.lcs.mit.edu> Cc: arch@FreeBSD.ORG Subject: Re: 64 bit counters again Message-ID: <20020121125522.G72285@gsmx07.alcatel.com.au> In-Reply-To: <200201202251.g0KMpq032842@khavrinen.lcs.mit.edu>; from wollman@khavrinen.lcs.mit.edu on Sun, Jan 20, 2002 at 05:51:52PM -0500 References: <mit.lcs.mail.freebsd-arch/3C48A0E7.F97BC01@mindspring.com> <200201190350.g0J3oNN08944@khavrinen.lcs.mit.edu> <3C48FCEF.9190CA08@mindspring.com> <20020121082826.Z72285@gsmx07.alcatel.com.au> <200201202251.g0KMpq032842@khavrinen.lcs.mit.edu>
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On 2002-Jan-20 17:51:52 -0500, Garrett Wollman <wollman@khavrinen.lcs.mit.edu> wrote: ><<On Mon, 21 Jan 2002 08:28:27 +1100, Peter Jeremy <peter.jeremy@alcatel.com.au> said: > >> 64-bit equivalents to the above IA32 instruction are: >> IA32: >> movl mem,%eax >> movl 4+mem,%edx >> 1: movl reg_lo,%ebx >> movl reg_hi,%ecx >> addl %eax,%ebx >> adcl %edx,%ecx >> lock cmpxchg8b mem >> jnz 1b > >Actually, that local label needs to be two instructions earlier. According to the Intel Architecture Software Developer's Manual, volume 2 (1999 - order 243191), cmpxchg8b is defined as "compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX". Based on this, the initial move doesn't need to be repeated because it's embedded in the "fail" case of cmpxchg8b. The label may need to be before the initial load for other compare-and-swap implementations. > The >beauty of this instruction sequence is that it is also atomic with >respect to interrupts on the local processor. I think that's also true of all the atomic sequences. Definitely an interrupt will release the lock on an Alpha ldq_l/stq_l sequence (and make it take an extra pass thru the loop). >> I don't know SPARCv9 or IA64, so can't comment on those, but from >> Garrett's comments, the IA64 code is similar to the IA32 code and >> the SPARCv9 code is similar to the Alpha code. > >Actually, the SPARC would be similar to the Intel. I think only Alpha >and MIPS implemented the LL/SC version of this primitive. Sorry about that. I mis-read your mail. Peter To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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