Date: Mon, 11 Mar 2019 19:15:57 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r345021 - head/contrib/llvm/lib/CodeGen Message-ID: <201903111915.x2BJFvFR059023@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: dim Date: Mon Mar 11 19:15:57 2019 New Revision: 345021 URL: https://svnweb.freebsd.org/changeset/base/345021 Log: Pull in r355854 from upstream llvm trunk (by Jonas Paulsson): [RegAlloc] Avoid compile time regression with multiple copy hints. As a fix for https://bugs.llvm.org/show_bug.cgi?id=40986 ("excessive compile time building opencollada"), this patch makes sure that no phys reg is hinted more than once from getRegAllocationHints(). This handles the case were many virtual registers are assigned to the same physreg. The previous compile time fix (r343686) in weightCalcHelper() only made sure that physical/virtual registers are passed no more than once to addRegAllocationHint(). Review: Dimitry Andric, Quentin Colombet https://reviews.llvm.org/D59201 This should fix a hang when compiling certain generated .cpp files in the graphics/opencollada port. PR: 236313 MFC after: 1 month X-MFC-With: r344779 Modified: head/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp Modified: head/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp ============================================================================== --- head/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp Mon Mar 11 19:10:48 2019 (r345020) +++ head/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp Mon Mar 11 19:15:57 2019 (r345021) @@ -14,6 +14,7 @@ #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -398,6 +399,7 @@ TargetRegisterInfo::getRegAllocationHints(unsigned Vir const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI = MRI.getRegAllocationHints(VirtReg); + SmallSet<unsigned, 32> HintedRegs; // First hint may be a target hint. bool Skip = (Hints_MRI.first != 0); for (auto Reg : Hints_MRI.second) { @@ -411,6 +413,10 @@ TargetRegisterInfo::getRegAllocationHints(unsigned Vir if (VRM && isVirtualRegister(Phys)) Phys = VRM->getPhys(Phys); + // Don't add the same reg twice (Hints_MRI may contain multiple virtual + // registers allocated to the same physreg). + if (!HintedRegs.insert(Phys).second) + continue; // Check that Phys is a valid hint in VirtReg's register class. if (!isPhysicalRegister(Phys)) continue;
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201903111915.x2BJFvFR059023>